Connecting leaders within the semiconductor eco-system

Keynote Speaker

Dr. Prof. Shaojun Wei / 魏少军

Professor of Institute of Microelectronics / 教授
Tsinghua University / 清华大学微电子学研究所

Biography / 魏少军教授简介

Prof. WEI received Master degree in Engineering from the Department of Radio and Electronics, Tsinghua University, Beijing, China in 1984 and Doctor degree in Applied Science in 1991 from the Laboratory of Electronics, Faculté Polytechnique de Mons, Belgium and then became the assistant professor in the same laboratory. From 1989 to1991, he also worked as a research fellow in ARAMIS, Belgium. Dr. WEI returned to China in 1995. From 1998 to 2005, he worked for Datang Telecom Technology Co., Ltd. successively as Vice-President, President & CEO. He was the founder, President & CEO and Chairman of the Board of Datang Microelectronics Technology Co., Ltd. from 1996 to 2005. He was the CTO of Datang Telecom Industry Group from 2005 to 2006.

Dr. WEI is now professor of Tsinghua University and adjunct professor of Peking University. Dr. WEI is the Vice President of CSIA, President of VLSI fables chapter, CSIA. He is the fellow of CIE and the fellow of IEEE.

The research interests of Dr. WEI are VLSI design methodology, communication specific IC development, mobile computing and reconfigurable computing. He has published more than 200 papers in above area.

Dr. WEI has won many awards during last years, including the National 2nd Prize for Advanced Technology in 2002; the National 2nd Prize for Technology Invention in 2015; Beijing 1st and 2nd Prize for Advanced Technology in 2001 and 2004; the Award for Outstanding Chinese Patented Invention, State Intellectual Property Office of China & World Intellectual Property Organization in 2004; the Outstanding Founder in ZhongGuanCun Science Park in 2001 and the Outstanding Leading Person in Semiconductor Industry, CSIA in 2003; China ACE Award – Lifetime Achievement Award of China Semiconductor Industry, Global Source, in 2014; 2018 China IC Design Award – Outstanding Contributor to China IC Industry, EETIMS; 2018 World Electronics Achievement Award – Contributor of the year, ASPENCORE；SEMI Special Contribution Award, IEEE 2020 CAS Industrial Pioneer Award, etc.

魏少军教授简介

魏少军，应用科学博士，百千万人才工程国家级人选，享受国务院特殊津贴专家。现任清华大学和北京大学双聘教授；“核高基”国家科技重大专项技术总师；国家集成电路产业发展咨询委员会委员；中国半导体行业协会副理事长，中国半导体行业协会集成电路设计分会理事长；世界半导体理事会中国JSTC主席；中国电子学会会士（CIE fellow）；国际电气和电子工程师学会会士（IEEE fellow）。

魏少军1984年在清华大学无线电系获工学硕士学位，1991年在比利时蒙斯理工大学微电子学实验室获应用科学博士学位。1992至1995年任比利时蒙斯理工大学助理教授，1995年10月回国工作。魏少军博士曾长期在工业界工作，先后担任过大唐微电子技术有限公司总经理、董事长；大唐电信科技股份有限公司总裁兼首席执行官；大唐电信科技产业集团总工程师。

魏少军教授长期致力于超大规模集成电路设计方法学的研究、可重构计算架构研究和通信专用集成电路技术研究。主要研究领域包括超深亚微米集成电路设计方法学研究，高层次综合技术研究，嵌入式系统设计技术研究和可重构计算技术研究。在上述领域发表了200余篇论文，拥有数十项中国和美国发明专利，出版专著五册。

魏少军教授先后获国家科技进步二等奖，国家技术发明二等奖；教育部技术发明一等奖（2项）；北京市科学技术进步一等奖；中国电子学会技术发明一等奖（2项）；国家知识产权局和世界知识产权组织专利金奖（2项）；及全国五一劳动奖章；中国科协“求是”杰出青年奖；“2003中国半导体企业领军人物”；SEMI特殊贡献奖；IEEE产业先驱奖等奖项和称号。

Topic

Could China balance the demand and supply of semiconductor products? / 中国能否平衡半导体产品的供需？

Abstract / 摘要

Since 2013, China has been the world’s largest importer of semiconductor products, with an annual import value of more than 200 billion US dollars. Since 2018, it has exceeded US $300 billion, about 75% of global semiconductor sales in that year.
Although China imports about 75% of global semiconductor products, a considerable part of them are installed in systems and exported to other countries in the world. About $150 billion of semiconductor products are consumed locally.
Correspondingly, although China’s domestic semiconductor industry has maintained a growth rate of about 20% in the past 10 years, the revenue of the domestic semiconductor products is only around 40 billion US dollars. In other words, the domestic products account for less than 30% of demand.
Facing the huge gap between demand and local supply, what measures China will take and what measures should be taken to develop the domestic semiconductor industry will not only be concerned the Chinese people, but also affect other countries in the world, especially in the current complex international environment.

2013年以来，中国已成为全球最大的半导体产品进口国，年进口额超过2000亿美元。2018年以来，更超过3000亿美元，约占当年全球半导体销售收入的75%。
虽然中国进口了全球75%的半导体产品，但其中相当一部分是安装在系统整机中出口到了世界其他国家。中国本地消费的半导体产品大约1500亿美元。
虽然中国国内的半导体产业在过去10年里保持了20%左右的年均复合增长速度，但国内半导体产品的全部收入只有400亿美元左右。换言之，国内产品仅能满足不到30%的需求。
面对巨大需求与本地供给的巨大差距，中国会采取什么措施及应该采取什么措施来发展国内半导体产业，不仅是国人关心的问题，也将影响到世界其他国家，尤其在当前复杂的国际环境下。

Terms & Conditions

1. Scope of Agreement

• These are the conditions of the contract between you, the Client (“You” and “your”) and China International Semiconductor Executive Summit (“CISES”, “we”, “us” and “our”) governing your use of our services, including event attendance as set out in your booking form. This agreement constitutes the entire agreement between CISES and you. All prior agreements understandings and negotiations and representations (save for fraudulent misrepresentation) whether oral or in writing are cancelled in their entirety. The terms of any other electronic communications will not form part of this agreement.

2. Our Commitment To You

• We will provide you with a planned schedule prior to the Event. Please note that this schedule may be altered where necessary by us.
• We reserve the right to determine the theme, scope and content of seminars and presentations to be held during the Event and to vary the programme and / or its contents as deemed necessary.
• Should the event be cancelled or the location be changed for reasons or circumstances beyond our control we reserve the right to reschedule the Event, including changing the location, and / or withdrawing delegates attendance upon written notice to you. If your attendance is withdrawn by us you will receive a full refund of your registration fee.

3. Delegates

• Only named or pre-agreed delegates may attend the Event. Non–appearance of any of the Delegates will not affect your obligation to pay in accordance with the terms set out below (5). No persons other than those officially registered or agreed with us may attend any part of the Event.
• Delegates must adhere to the deadlines set out by the Operations Manager. Deadlines will be communicated once we have received your delegate contract confirmation. This includes returning your catalogue entry form, delegate photograph and your prioritised meeting request choices.
• Delegates must attend all prescheduled Event meetings and the seminar programme.
• Delegates are responsible for their own insurance (including, but not limited to, travel insurance, personal effects and personal insurance), vaccinations and visas (where applicable).

4. Flights / Hotel – Airport Transfers / Accommodation

• Delegates are responsible for their own flight, transfer arrangements and accommodation and the costs associated with them.

5. Payment

• The total fees specified on the Agreement are subject to an additional service charge of 7.5% (“Service Charge”) applied to cover administration costs, and are exclusive of VAT and any other applicable sales tax which shall be payable in addition.
• Payment must be received in full within 28 days from the date of this agreement.
• The applicable VAT rate will be charged in addition to the Total Cost.
• Contracts received within 28 days of the start of the event must be paid by return.

6. Cancellation

• Cancellations received more than twelve weeks prior to the Event commencement date will be entitled to a full refund of the registration fee paid.
• If you cancel your registration less than twelve weeks before the Event commencement date you will incur a charge of £1,500 (less any registration fee, as specified on this registration form, that you may have already paid which will not be refunded).
• Cancellation fees can be avoided by providing replacement delegates from your organisation. You will be liable for any additional cost incurred as a result of supplying replacement delegates. We reserve the right to refuse replacement delegates.
• All cancellations must be received in writing and agreed by us, and full cancellation fees must be paid within 14 days.

7. General

• You the delegate, your executive/s or your agents may not transfer or assign any of the rights or obligations of this Agreement (in whole or part) without our prior consent. Any attempt to resell, assign or transfer rights without our consent will entitle us to cancel the contract without liability to you.
• CISES is subject to the UK Data Protection Act 1998 and is registered in the UK with the Information Commissioner t o process your personal information. Our primary goal in collecting personal information from you is to give you an enjoyable customised experience whilst allowing us to provide services and features that most likely meet your needs. We collect certain personal information from you, which you give to us when using our Sites and/or registering or subscribing for our products and services. We also collect certain personal data from other group companies to whom you have given information through their websites. If you do not want us to continue using this information please notify us at enquiries[at]ioctr.com. Any personal information supplied to CISES as part of this registration process and/or any other interaction with CISES will be collected, stored and used by CISES, its subsidiaries, related companies or affiliates in accordance with the CISES Privacy Policy. Please email enquiries[at]ioctr.com for a copy of the CISES Privacy Policy.
• This agreement is governed by and will be construed in accordance with English law and each party irrevocably agrees that the courts of England will have the non-exclusive jurisdiction to deal with any disputes arising out of or in connection with this agreement.
• The working language of the Event is English. Delegates requiring an interpretation service must make their own arrangements at their own expense.

Daniel Graf

Head of Business Development, 0eC

Biography

Daniel Graf is Head of Business Development at 0eC. Mr. Graf is mainly responsible for marketing and investor relations and organises the public presentation of 0eC. Prior to his work with 0eC, he was working in the telecommunication and automotive branch as a system engineer and a freelance IT consultant for more than 10 years, and he has worked in projects for process analysis and customisable system administration. In 2015, he founded a consulting company, Freimuth & Graf Consulting UG, which focuses on methods to build reliable, scalable companies. He has engaged in several startup projects, including AI and app development, where he has implemented agile methods and taken the lead in company building. Through his experience in these projects, Mr. Graf has become an advisor for an investment fund, where he mainly consults in tech investment cases.

In January 2019, he joined ZeroEC as Head of Business Development and started to convert the scientific physical breakthrough that Erez Halahmi’s team have achieved into a startup that will change the fundamental principles of data transfer.

Topic

A new approach to reach 25 Tbps/mm and more

Abstract

ZeroEC technology replaces the current electric conductors with a patented technology that enables the use of free electrons for data transport in semiconductor applications. Unlike copper, our technology makes it possible to transmit the information from the sending unit to the receiving unit in microscopic bundles, using approximately only 100 electrons per bit, compared to the +10,000-100,000 electrons that are needed to charge the metal in conventional copper conductors – and without the need for conversion, as in fibre optics.

免责声明

中国国际半导体高管峰会已尽最大努力确保本网站讯息的准确性和最新性，对于本网站的内容和其中描述的产品和服务，包括但不限于准确性、完整性、非侵权性、适销性、特定用途的适用性或可用性，中国国际半导体高管峰会不承担任何形式的损失或损害责任，包括因传输或下载而感染计算机病毒。

本网站的内容可能随时更改，恕不另行通知。 提供其他网站的连接是为了方便用户。中国国际半导体高管峰会不对这些网站的内容或属性发表意见，也不承担任何相关责任。 本网站上包含的讯息不构成产品或服务的提供。 投资者不得依赖本网站提供的讯息进行投资决策。

免責聲明

中國國際半導體高管峰會已盡最大努力確保本網站訊息的準確性和最新性，對於本網站的內容和其中描述的產品和服務，包括但不限於準確性、完整性、非侵權性、適銷性、特定用途的適用性或可用性，中國國際半導體高管峰會不承擔任何形式的損失或損害責任，包括因傳輸或下載而感染電腦病毒。

本網站的內容可能隨時更改，恕不另行通知。提供其他網站的連接是為了方便用戶。中國國際半導體高管峰會不對這些網站的內容或屬性發表意見，也不承擔任何相關責任。本網站上包含的訊息不構成產品或服務的提供。投資者不得依賴本網站提供的訊息進行投資決策。

条款及细则

1.协议范围

• 这些是您，客户，与中国国际半导体高管峰会（” CISES”）之间关于您使用我们的服务的合同的条件， 包括预订表中列出的活动出席人数。 该协议构成CISES与您之间的全部协议。 先前所有口头或书面协议的理解，谈判和陈述（欺诈性的虚假陈述除外）均完全取消，任何其他电子通信的条款均不构成本协议的一部分。

2.我们对您的承诺

• 我们将在活动前向您提供一份计划时间表。 请注意，我们可能会在必要的情况下更改该时间表。
• 本公司保留在活动期间举行的研讨会和演讲的主题、范围和内容的决定权利，并在认为有需要时更改节目和/或其内容。
• 如果活动因我们无法控制的原因或情况而取消或改变地点，我们保留重新安排活动的权利，包括更改地点和/或在书面通知您后撤回代表出席。 如果你的出席被我们取消，你将收到全额退费。

3.出席代表

• 只有指定或预先约定的代表才可出席活动。 任何代表不出席并不影响您根据以下条款（5）支付费用的义务。 除经正式登记或与本公司达成协议的人士外，其他人士不得出席活动的任何部分。
• 代表们必须遵守营运经理指定的截止日期。 我们将在收到您的代表合同后通知您截止日期，这包括交回您的目录登记表、代表照片和您的优先会议请求选择。
• 代表们必须参加所有预先安排的活动会议和研讨会方案。
• 代表们需负责自己的保险（包括但不限于旅行保险，个人财物和个人保险），疫苗接种和签证（如适用）。

4.航班/酒店–机场接送/住宿

• 代表们需自行负责航班，中转安排和住宿及与之相关的费用。

5.付款

• 该协议规定的总费用需支付7.5%的额外服务费（”服务费”），用于支付行政成本，并且不包括增值税和任何其他适用的销售税。
• 必须在本协议签订日起28天内全额收到付款。
• 除总费用外，还将收取适用的增值税税率。
• 活动开始后28天内收到的合同必须以退款方式支付。

6 .取消

• 在活动开始前12周以上取消报名，将有权全额退还已支付的报名费。
• 如果您在活动前12周内取消报名，将产生1500英镑的费用（减去报名表上注明的任何报名费，您可能已经支付的费用将不予退还）。
• 您可以通过提供贵公司的替代代表来避免取消造成的费用。您将承担因提供替代代表而产生的任何额外费用。我们保留拒绝替代代表的权利。
• 所有的的取消报名必须以书面形式通知并经我们同意，并且必须在14天内支付全额取消费。

7.一般

• 未经我们事先同意,您,代表,执行人员或代理人不得全部或部分转让本协议的任何权利或义务。未经我们同意，任何转售，转让或转让权利的尝试都将使我们有权取消合同，而对您不承担任何责任。
• 中国国际半导体高管峰会受《1998年英国数据保护法》的约束，并在英国的资讯专员处注册，以处理您的个人资料。我们搜集您的个人资料的主要目的是给您提供一个愉快的客制化体验，同时让我们提供最能满足您需求的服务和功能。我们会由这些信息是您在使用我们的网站和/或注册或订阅我们的产品和服务时所提供的提供资讯，来搜集您的个人讯息。如果您不希望我们继续使用这些资讯，请通知我们：enquiries@ioctr.com。任何提供给中国国际半导体高管峰会的个人信息作为注册过程的一部分和/或与中国国际半导体高管峰会的任何其他互动，将由中国国际半导体高管峰会、其子公司、相关公司或关联公司按照中国国际半导体高管峰会隐私政策搜集、储存和使用。请发送电子邮件至enquiries@ioctr.com获取中国国际半导体高管峰会隐私政策的副本。
• 本协议受英国法律管辖，并根据英国法律进行解释，各方均不可撤销地同意，英格兰法院将具有非排他性管辖权来处理因本协议引起的，或与本协议有关的任何争议。
• 本活动的工作语言是英语。需要口译服务的代表必须自行安排，费用自理。

Disclaimer

While great efforts were made to ensure accurate and up-to-date information on this website, China International Semiconductor Executive Summit makes no representations or warranties whatsoever, express or implied, as to the content of this website and the products and services described therein, including, without limitation, with respect to accuracy, completeness, non-infringement, merchantability, fitness for a particular purpose, or availability, and China International Semiconductor Executive Summit disclaims any liability for losses or damages of any kind, including losses or damages resulting from the transmission or downloading of computer viruses.

The content of this website may be changed at any time without notice. Links to other websites are provided for the user’s convenience. China International Semiconductor Executive Summit does not express an opinion on the content or the properties of such linked websites and disclaims any liability in connection therewith. The information contained on this website does not constitute an offer for products or services. Investors must not rely on information provided on this website for investment decisions.

條款及細則

1. 協議範圍

• 這些是您，客戶，與中國國際半導體高管峰會（“ CISES”）之間關於您使用我們的服務的合同的條件， 包括預訂表中列出的活動出席人數。 該協議構成CISES與您之間的全部協議。 先前所有口頭或書面協議的理解，談判和陳述（欺詐性的虛假陳述除外）均完全取消，任何其他電子通信的條款均不構成本協議的一部分。

2.我們對您的承諾

• 我們將在活動前向您提供一份計劃時間表。請注意，我們可能會在必要的情況下更改該時間表。
• 本公司保留在活動期間舉行的研討會和演講的主題、範圍和內容的決定權利，並在認為有需要時更改節目和/或其內容。
• 如果活動因我們無法控制的原因或情況而取消或改變地點，我們保留重新安排活動的權利，包括更改地點和/或在書面通知您後撤回代表出席。如果你的出席被我們取消，你將收到全額退費。

3.出席代表

• 只有指定或預先約定的代表才可出席活動。任何代表不出席並不影響您根據以下條款(5)支付費用的義務。除經正式登記或與本公司達成協議的人士外，其他人士不得出席活動的任何部分。
• 代表們必須遵守營運經理指定的截止日期。我們將在收到您的代表合同後通知您截止日期，這包括交回您的目錄登記表、代表照片和您的優先會議請求選擇。
• 代表們必須參加所有預先安排的活動會議和研討會方案。
• 代表們需負責自己的保險（包括但不限於旅行保險，個人財物和個人保險），疫苗接種和簽證（如適用）。

4.航班/酒店–機場接送/住宿

• 代表們需自行負責航班，中轉安排和住宿及與之相關的費用。

5.付款

• 該協議規定的總費用需支付7.5%的額外服務費（”服務費”），用於支付行政成本，並且不包括增值稅和任何其他適用的銷售稅。
• 必須在本協議簽訂日起28天內全額收到付款。
• 除總費用外，還將收取適用的增值稅稅率。
• 活動開始後28天內收到的合同必須以退款方式支付。

6.取消

• 在活動開始前12週以上取消報名，將有權全額退還已支付的報名費。
• 如果您在活動前12週內取消報名，將產生1500英鎊的費用（減去報名表上註明的任何報名費，您可能已經支付的費用將不予退還）。
• 您可以透過提供貴公司的替代代表來避免取消造成的費用。您將承擔因提供替代代表而產生的任何額外費用。 我們保留拒絕替代代表的權利。
• 所有的取消報名必須以書面形式通知並經我們同意，並且必須在14天內支付全額取消費。

7.一般

• 未經我們事先同意，您，代表，執行人員或代理人不得全部或部分轉讓本協議的任何權利或義務。 未經我們同意，任何轉售，轉讓或轉讓權利的嘗試都將使我們有權取消合同，而對您不承擔任何責任。
• 中國國際半導體高管峰會受《 1998年英國數據保護法》的約束，並在英國的資訊專員處註冊，以處理您的個人資料。我們蒐集您的個人資料的主要目的是給您提供一個愉快的客制化體驗，同時讓我們提供最能滿足您需求的服務和功能。我們會由這些信息是您在使用我們的網站和/或註冊或訂閱我們的產品和服務時所提供資訊，來搜集您的個人訊息。如果您不希望我們繼續使用這些資訊，請通知我們：enquiries@ioctr.com。任何提供給中國國際半導體高管峰會的個人信息作為註冊過程的一部分和/或與中國國際半導體高管峰會的任何其他互動，將由世界太陽能大會、其子公司、相關公司或關聯公司按照中國國際半導體高管峰會隱私政策搜集、儲存和使用。請發送電子郵件至 enquiries@ioctr.com 獲取中國國際半導體高管峰會隱私政策的副本。
• 本協議受英國法律管轄，並根據英國法律進行解釋，各方均不可撤銷地同意，英格蘭法院將具有非排他性管轄權來處理因本協議引起的，或與本協議有關的任何爭議。
• 本活動的工作語言是英語。 需要口譯服務的代表必須自行安排，費用自理。

Mustafa Badaroglu

Principal engineer and architect, IRDS More Moore Global Chair, IEEE,
Qualcomm

Biography

Dr. Mustafa Badaroglu is Principal Engineer and Architect at Qualcomm responsible from technology and architecture definition and development for products employing Compute-In-Memory Technology. Before rejoining Qualcomm, he previously worked at Huawei, Qualcomm, IMEC, ON Semiconductor, and Tubitak Space. During his career he had various assignments for the execution and management of mobile, server, and automotive chipset designs from concept to volume production, process technology pathfinding, electronic design automation, and design-technology co-optimization. Dr. Badaroglu received his Ph.D. in Electrical Engineering and holds a Master of Industrial Management, both from the Catholic University of Leuven. He holds more than 60 published patents and (co)-authored over 100 publications in scientific journals/proceedings. He is the global chair of IRDS More Moore Team focusing on HVM roadmap of logic devices and memory. He is a senior member of IEEE.

Topic

More Moore roadmap for high-performance computing enablement – IRDS view

Abstract

We are living in a connected world with access to data in vast amounts. We now need to make this data connectivity more intelligent and accessible. This could for instance include more intelligent sensors and human-computer interfaces bringing people closer to the computation in a more natural and accessible way. Instant data generation requires ultra-low-power devices with an ìalways-onî feature at the same time with high-performance devices that can generate the data instantly. Big data requires abundant computing, communication bandwidth, and memory resources to generate the service and sensible information that people need. In this presentation we will talk about the More Moore technology enablement items for HPC and AI computing in the next 15 years.

Marco Giandalia

VP IC Design Engineering, Navitas Semiconductor

Biography

Marco serves as Vice President Engineering / IC Design for Navitas Semiconductor and has over 20 years’ experience in the field of Power IC product and technology development in Si and GaN since he received is MSEE in 1996.

Before joining Navitas, Marco led the Energy Saving Product – Design Center at International Rectifier developing innovative products for Off-Line application like motor drive, AC/DC, DC/DC converters. Earlier he was in charge as IC Design Engineer at STMicroelectronics for Smart Power IC product line.

He has been granted several patents for Power IC design solutions and has been author of multiple papers and conferences presentations.

Topic

GaNFast Power IC for AC/DC power converter

Abstract

Aim of this presentation is to introduce a new class of GaN devices and explore all the potential benefits they can provide in a specific range of applications. The new class of devices consist of a 650V Enhanced Mode Monolithic (All-GaN) Power IC targeting ultra-high frequency AC/DC power adapter.

They are designed to offer low RdsON and an unprecedented ease of use and efficiency performance, fully exploiting GaN device capability. The industry’s first monolithic GaN Power IC has all the features necessary for the next generation of high density and high efficiency AC-DC chargers and adapters. Traditional topologies using silicon FETs have reached their limits and GaN Power ICs enable more advanced, soft-switching topologies to operate at 20x higher frequency with increased efficiency and very high power density. GaN Power ICs use lateral enhancement mode (eMode) HEMT technology to overcome the traditional gate driving complexity

The key to GaN’s game-changing attack on silicon is true, monolithic integration – combining GaN FET, GaN logic and GaN analog circuits to achieve a ‘digital-in, power-out’ MHz building block. Monolithic integration enables high-frequency power conversion and the ability to shrink passive components like transformer, EMI filters, output capacitors – to deliver solutions that can charge 3x faster in half the size and weight of old, slow, silicon solutions.

GaN the game-changer is fast, very fast and we will see fast adoption across all markets from fast chargers to all-in-one PCs, TVs, multi-kW server, eMobility and new energy markets.

Tim Olson

CEO, DECA

Biography

Tim Olson is founder, CEO and a director of Deca Technologies, Inc. Tim has served in both CEO and CTO roles as Deca has established its industry leading M-Series™ fan-out and Adaptive Patterning™ technologies.

Tim was previously Sr. VP of Global Research & Development and Emerging Technologies at Amkor as well as EVP of Products and Operations at Micro Component Technology. Tim started his career in semiconductors at Motorola where he led creation of PRISM, an advanced assembly and test CEO model factory, which delivered two major innovations to the semiconductor industry: strip-based final test and integrated 2D codes for product tracking and traceability.

Tim graduated magna cum laude from UND with bachelor’s degrees in mechanical engineering and engineering management. Tim holds over two dozen issued United States patents relating to packaging, software, equipment, process, and design.

Babak Sabi

General Manager, Intel Corp.

Biography

Babak Sabi is the Corporate Vice President and General Manager of Assembly and Test Technology Development. Since 2009, he has been responsible for the company’s packaging assembly process, packaging materials, enabling assembly and test technology development.  Sabi joined Intel in 1984.

Prior to leading ATTD, Sabi led the Corporate Quality Network within Intel’s Technology Manufacturing Group from 2002 to 2009. He led a company-wide network of quality and reliability organizations responsible for product reliability customer satisfaction and quality business practices.

Previously,  Sabi managed technology development quality and reliability and was responsible for silicon technology certification, assembly, test, and board processes.

Sabi received his Ph.D.in solid-state electronics from Ohio State University in 1984. He has written 10 papers on reliability physics and has received 5 Intel Achievement Awards.  He currently holds 2 patents.

Title

Advanced Packaging Architectures: Scaling for A Heterogeneous World

Abstract

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems.  As a result, several innovative packaging architectures have been announced in recent years.  On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits.  In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be (1) interconnect scaling, (2) power efficient high bandwidth signaling, (3) cost-optimized cooling and (4) advanced power delivery technologies.  The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization and supply chain development.

Wim Renirie

VP and GM for BL AWS, ams

Biography

Born in the Netherlands Wim got his PhD in electrical Engineering from the Technical University in Delft. He holds 2 US patents. He has over 25 years of experience in the semiconductor industry where he held different positions in development, marketing and management in the fields of Audio and Video, analog and digital TV reception, 4G and 5G communication and WiFi. Wim worked with companies such as Micronas, Trident and NXP and joined ams in 2019 as VP and GM of BL Accessory and Wearable Solutions covering innovations and product developments in the area of Vital, Spectral and Audio.

Topic

Spectral sensing enabled Digital Lateral Flow Test- Fast, Objective, Easy to use, Cloud based.

Abstract

The entire world got disrupted early this year with the Covid-19 virus spreading all over the place. To control the spreading of the pandemic, entire countries went into lock-down with enormous personal and economic consequences. We are now facing the start of the second wave and it is extremely important to have regional and fast insight into the spreading of the virus to minimize impact.  ams’ novel Digitized Lateral Flow Test will enable fast, objective results that give very early insight on outbreaks. It shows how the combination of innovation in consumer electronics using spectral sensing with the medical world can make a big change.

Mario Morales

Program Vice President, IDC

Biography

Mario Morales is the program vice president of IDC’s enabling technologies, storage, and semiconductor research. He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and consumer.

Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.

Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, IBM, GE software, SoftBank, ARM, NXP, and others.

Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.

Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage and memory,sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, accelerated computing architectures, cellular baseband modems, WLAN, WiMAX, cellular broadband, digital consumer, foundry, EMS, intelligent systems, and overall semiconductors.

His career includes past postions with NEC Electronics and Dataquest.

EDUCATIONAL ACCOMPLISHMENTS

• B.S. in Finance and Accounting from San Jose State University
• Fluent in English and Spanish
• Frequent presenter and advisor to CEOs and executive teams across his portfolio of clients
• Strong reputation as an advisor and industry expert on Wall Street
• IDC executive analyst for Intel and Qualcomm
• Frequent speaker, presenter, and moderator at IDC Directions events in Asia and semiconductor industy conferences including ISS, GSA, CASPA, and SEMI

Topic

Semiconductor Market Perspective and Outlook: COVID Impact to Investment, Innovation, and Growth

Abstract

Key discussion questions:

• How sustainable has the recovery been for semiconductor suppliers this year in spite of COVID?
• How is the supply chain adapting to consolidation of leading edge process technology?
• What is our perspective on the NVIDIA arm acquisition?

Semiconductor content is growing across all major markets. As we look forward there are some exciting technologies that begin to ramp over the coming years, including 5G, WiFi 6, AI inferencing, NAND, advanced process technologies and packaging, and optimized computing at the edge that will drive a sustainable recovery for the industry.  What will be the inflection point of each market? Who are the key technology suppliers that stand to gain from the revenue growth over the coming years?

Mr. Morales will share his perspective on these key questions and provide guidance to technology companies in order to capitalize on the opportunities in store for the semiconductor industry over the next five years.

Dr. James Ong / 翁家良

MD and Co-Founder / 院长与联合创始人
AI International Institute / 人工智能国际研究院

Biography

Dr James Ong is Managing Director and Co-Founder of Artificial Intelligence International Institute (AIII), a think tank focusing on Sustainable AI. AIII actively engage in the AI ecosystem development including Slingshot 2020 @ SFF x SWITCH, the World AI Conference (WAIC) SAIL Award, IBM Call for Code Hackathon, Shanghai AI
Development Alliance (SAIA)., Singapore’s AI Professionals Association (AIP) and Singapore Lean Launchpad. James is also an entrepreneur, community builder and adjunct professor at SUTD (Singapore University of Technology and Design). He has incubated, invested and mentored various technology startups in China, Singapore and
USA and has more than 30 years of experience in the technology and strategy advisory services in Asia, US and Europe where he has advised many Fortune 500 companies on enterprise digital transformation across multiple generations of technology evolution. James received his PhD in Management Information System and MA & BA in Computer
Science from the University of Texas at Austin.

AIII人工智能国际研究院院长与联合创始人 工信部电子标准院国家AI标准化总体组专家成员 新加坡科技与设计大学特聘教授 世界知名美国MCC研究院科学家 美国德克萨斯大学奥斯汀分校信息化系统管理博士 在中国，新加坡，美国和欧洲拥有30年以上丰富的科技产业/创业/科研经验 提供企业级科技数字化转型策略咨询给500强企业.。

Topic

Towards Sustainable AI / 迈向可持续人工智能

Abstract

Even since the 1956 Darmouth College workshop hosted by AI pioneers including John McCarthy, Marvin Minsky, Herbert Simon, Allen Newell etc., AI has gone through 2 waves of industry adoption. The first wave was in 1980s with Japan’s Fifth Generation Computer Project based on Symbolic Logic and Knowledge-based paradigm and the current wave was triggered in 2015 with Deepmind’s AlphaGo breakthrough based on Machine Learning and Deep Learning paradigm. The first wave did not last and resulted in AI winter. There are plenty of lessons to be learned on how all the stakeholders should collaborate to ensure a sustainable development of the AI ecosystem and focus on areas where we should innovate towards a future with Sustainable AI.

Dr. Wei Li / 李炜

EVP of National Silicon Industry Group, Chairman of Zing Semiconductor Corporation & SIMGUI Technology
上海硅产业集团股份有限公司执行副总裁、上海新昇及新傲科技董事长

Biography

Dr. Li Wei graduated in 1994 from the Department of Mechanical Engineering, Tsinghua University and received his Master’s Degree of Materials Engineering in 1997 from Zhejiang University, followed by his Ph.D in 2000 from the Microelectronics at Shanghai Institute of Metallurgy CAS.

Dr. Li participated in the establishment of Simgui and has served many roles in that company since 2001, including: Assistant to the President; Vice President; and Secretary of the Board. Since 2017, Dr. Li has been the Chairman of Simgui.

Dr. Li assisted in the launch of Zing Semiconductor in 2014, and has also served multiple roles there, including: Board Member, Co-CEO and Legal Representative. From May 2019, he has been the Chairman of Zing Semiconductor.

Dr. Li also helped to initiate the founding of NSIG and served as EVP of the company. From 2017, he continues in his role as the Secretary of the Board of Directors.

Dr. Li was awarded the 1st Class Reward of National Technology Improvements, First Prize of Shanghai Science and Technology Progress Award, and Outstanding Scientific Achievement Reward. He was selected as Shanghai Model Worker and to the National Ten Thousand Talent Program in 2016. Dr. Li has been responsible for many national / local scientific research and industrialization projects.

Dr. Li also serves as Vice President of China Semiconductor Industry Association (CSIA) as well as Vice President of IC MTIA.

1994年李炜博士毕业于清华大学机械工程系，1997年获浙江大学材料工程硕士学位，2000年获中国科学院上海冶金所微电子学博士学位。

李炜博士于2001年参与发起创立上海新傲科技股份有限公司，历任总经理助理、副总经理，兼任董事会秘书。2017年3月起担任新傲科技董事长。

2014年协助发起创立上海新昇半导体科技有限公司，历任董事、联席CEO兼法定代表人。2019年5月起担任上海新昇董事长。

2015年12月参与发起设立上海硅产业集团股份有限公司，任硅产业集团执行副总裁，2017年起兼任董事会秘书。

李炜博士荣获国家科技进步一等奖、上海市科学技术进步一等奖、中国科学院杰出科技成就奖等，2010年被评为上海市劳动模范，并于2016年入选中组部第二批国家“万人计划”。李炜博士曾主持或参与了包括02专项在内的多项国家或上海市重大科研或产业化项目。

李炜博士担任中国集成电路行业协会支撑业分会副理事长，中国集成电路材料产业技术创新联盟副理事长。

Topic

An Opportunity for 300 mm Silicon Wafers in China / 中国制造300毫米硅片的机遇

Abstract

The semiconductor industry continues to play a key role in the global economy and is a foundation of modern livelihood. Today’s silicon wafer, particularly 300mm, is effectively the foundation of semiconductors.

Although macroeconomic challenges continue to arise, the industry remains dedicated to advancement. Collaboration, more than ever, is critical to progress. NSIG and Zing Semiconductor, as an entrant in 300 mm silicon wafer production having the necessary funding, technology, talent and understanding, are committed to cooperate with our customers and the industry to realize this success.

半导体产业在全球经济中继续发挥关键作用，是现代社会生活的基础。 如今300mm硅片是半导体的基础材料。

尽管宏观经济挑战持续出现，但半导体行业仍致力于创新发展。 全球协作对于创新发展至关重要。 沪硅产业和新昇半导体作为 300 mm 硅片的新进，拥有必要的资金、技术、人才、

和行业积累，致力于与客户和业界合作，实现更大的成功。

Dr. Daquan Yu / 于大全

CEO, Xiamen Sky Semiconductor / 厦门云天半导体科技有限公司
Professor, Xiamen University / 厦门大学 / 特聘教授

Biography

Dr. Daquan Yu is a Distinguished Professor of Xiamen University and the CEO of Xiamen Sky Semiconductor Co., Ltd. He was the President of Research Academy of Advanced Packaging Technology of TSHT Group from 2014 to 2019. Before that, he was a professor of Institute of Microelectronics, Chinese Academy of Sciences from 2010 to 2015. He had carried out research work at Fraunhofer IZM in Germany, and Institute of Microelectronics in Singapore from 2005 to 2010. He has authored or co-authored more than 200 peer-reviewed technical publications and holds more than 70 patents. He is a member of the Expert Committee of the 02 National Science and Technology Major Program of China, vice president of MEMS branch of China Semiconductor Industry Association, and a Senior member of IEEE.

于大全，博士，厦门大学特聘教授、微电子与集成电路系主任，厦门云天半导体创始人。2014-2019年任天水华天科技公司封装技术研究院院长。2010-2015年担任中科院微电子所研究员。2004-2010年先后在香港城市大学、德国Fraunhofer IZM、新加坡微电子所等知名研究机构开展研究。长期从事先进微电子封装技术研究与产业化，发表学术论文200余篇，授权国家发明专利70多项。主要社会任职有：国家科技重大专项02专项总体组特聘专家，中国半导体行业协会MEMS分会副理事长，IEEE高级会员。

Topic

Progress of through glass via technology for 3D Wafer Level Packaging

Abstract

High density 3D Wafer level packaging using 2.5D interposer based on through silicon via (TSV) and wafer level Fan-In, Fan-Out technologies achieve great progress. With the coming of 5G era, new packaging technology suitable for high frequency are still needed. Through glass via (TGV) technology become attractive for 2.5D interposer, filters, IPDs, and RF modules. The advantages of wafer level TGV packaging technology include small form factor, low cost, simple process, and excellent electrical performance. The recent progress of TGVs for via formation, via filling and RDL formation are presented. In addition, the progress on the applications are discussed.

最近，基于2.5D硅通孔转接板，晶圆级扇入扇出、扇入技术的三维晶圆级高密度封装取得了巨大进步。随着5G的应用到来，需要多种新的适用于高频应用的封装技术。玻璃通孔技术对于2.5D 转接板、滤波器、无源器件和射频模块极具吸引力。晶圆级玻璃通孔封装技术的优点包括小型化，低成本，工艺流程简单，突出的电学性能。报告展示了最新的通孔制造、填充、再布线技术进展，讨论了相关产品应用。

Dr. Daping Yao / 姚大平

CEO & President (CASMEIT) / 总经理 (中科智芯)
Technical Director (NCAP China) / 资深技术总监（华进半导体)

Biography

Dr. Daping Yao joined NCAP China as a technical director in June 2017. He has been responsible for various R&D projects of wafer level packaging technologies including FOWLP. In order to build up a high-volume production facility dedicated to FOWLP, he founded Jiangsu CAS Microelectronics Integration Technology Co Ltd (CASMEIT) in March 2018 located in Xuzhou city, Jiangsu province. Currently Dr. Yao serves as the company’s CEO and president. Prior to his roles in China, Dr. Yao had been working for Applied Materials Inc., California, USA for more than 20 years in various roles, including development of semiconductor manufacturing processes and equipment.

Topic

Development of Wafer Level Packaging Technology: Fan-in, Fanout and 3D Integration / 从扇入、扇出到三维集成的晶圆级封装技术研发进展

Abstract

Wafer level packaging (WLP) technology has progressed rapidly though fan-in, fan-out, and 3D packages. We first look at the preferred fan-in WLP structures based upon reliability performance. Fanout wafer level packaging (FOWLP) technology has drawn industry’s attention tremendously since it was adopted into the mobile application. FOWLP enables wafer level system-in-package (SiP) during which multiple heterogenous chips are integrated into a reconstructed wafer to form a dedicated packaging module. Such a method balanced well the manufacturing cost and module performance with the smallest packages. 3D integration technology is the main solution that can meet the required performance of applications like AI and HPC.

NCAP-China and CASMEIT have started numerous WLP projects to study packaging design structure, reliability, materials verification, and process flows. We present some of our recent work on various applications, such as single chip packaging and multi-chip integration.

近来晶圆级封装 （WLP） 技术通过扇入、扇出和3维堆叠封装发展迅速。我们先比较基于可靠性的首选扇入式晶圆级封装结构，扇出型晶圆级封装（FOWLP）技术自从被智能手机应用以来，已引起业界的极大关注。FOWLP 支持晶圆级系统集成（SiP），包括多个异质芯片集成到重建的晶圆中，以形成专用的封装模块。这种方法能很好地平衡制造成本、模块性能、以及最小的封装体积。3D集成技术是满足 AI 和 HPC 等应用所需性能的主要解决方案。

华进和中科智芯已经启动很多WLP项目，研究包装设计结构、可靠性、材料验证和工艺流程。我们也将介绍我们最近在各种应用上的一些工作，例如单芯片封装和多芯片集成。

Dr. Min-hwa Chi / 季明华

SVP TD
SiEn Integrated Circuit Cor / 芯恩青岛集成电路

Biography / 季明华

Dr. Min-hwa Chi received his BS, MS, and Ph.D in EE at National Taiwan University, University of Rhode Island, and University of California -Berkeley (1982) respectively. He has served VLSI industry in Intel (1982-1988), KFI technology (1988-1994), and National Semiconductor (1994-97) in NVM, CMOS-Imager, and module process development. He served foundry industry for TSMC (1997-2005) as Sr. Director/R&D, Globalfoundries (2011-15) as Sr. Fellow/Dir, SMIC China (2006-2011， 2015-2018) and SiEn (QingDao) Integrated Circuits (2018~) as SVP/TD. He served as guest professor at Peking University (2010-11) and honorary professor at Fu-Dan University (2008-10) at China. He is IEEE Life Sr. member (2001). He has 257 US patents; published 3 books, and 100+ technical papers in areas of CMOS Logic/FinFET, Flash memory, CMOS Imager, DRAM, and Power devices.

季明华博士，从加州大学伯克利分校获得博士学位(1982)，拥有38年的国际半导体产业经验，专注于半导体先进技术的研发。曾发表过半导体技术期刊和会议论文99篇，合著书3册, 拥有美國专利257项, 国际专利超过550项。

季明华博士曾工作于Intel (1982-1989); KFI 技术（1989-1994），美国国家半导体 (1994-1997); 台湾积体电路Tsmc (1997-2005)任资深研发总监; GLOBAL-FOUNDRIES (2011-2015) 任资深技术专家/总监; 中芯国际（2006-2011, 2015-2018）, 和芯恩 (青岛) 集成电路 (2018 )任资深副总。负责20nm平面CMOS相关的技术开发，14nm FinFET技术的器件整合和模块工艺，并参与10nm/7nm FinFET的技术开发。

季明华博士曾获得台积电杰出专利奖、美国国家半导体公司创新奖、英特尔杰出成就奖等荣誉，并担任青岛大学 和北京大学“兼职教授”、中科院微电子研究所“荣誉教授”、复旦大学“荣誉教授”、美国IEEE终生资深会员等职务。

Topic / 题目

Smart Manufacturing for Si, SiC, GaN Power Devices in AI Era /  在人工智能时代，智能制造Si, SiC, 和GaN电力器件

Abstract / 摘要

Today’s IC technology at AI/IoT era drives all aspects of high-tech industry as nation’s strength. Power ICs and devices are progressed from Si to SiC and GaN based technologies and are also utilizing AI techniques extensively in product design (e.g. multi-level co-optimization, con-current design, failure analysis, and 3D packaging, etc.) as well as manufacturing (e.g. automation for thin wafer handling, defect/contamination control, etc.) toward superior performance, yield and reliability.

今日AI/IoT时代的IC技术，推动了高科技工业的所有层面，并展现为国家的力量. 电力ICs和器件也正从Si进步到SiC和GaN的技术；正在产品设计和制造上广泛地使用AI和大数据技术 (如:多层次并行优化, 并行设计, 失效分析, 3D封装, 等) 和生产制造 (e.g. 薄Si片处理的自动化, 缺陷/污染控制, 等) 以迈向极优异性能 , 良品率，和可靠性.

Keynote Speaker

Dr. Simon Yang / 杨士宁 博士

CEO, YMTC / 长江存储科技有限责任公司首席执行官

Biography

Dr. Simon Yang is the CEO of YMTC, who brings YMTC to a new height in 3D NAND industry. As an experienced executive in the semiconductor industry for over 30 years, Simon served as the CEO of XMC, COO/CTO of SMIC, and CTO/SVP of Chartered Semiconductor (Now GlobalFoundries), in charge of fab operation and technical R&D. Before that, he was in the Portland Technology Development sector of Intel for more than 10 years, in which he led a series of technical R&D projects.
Simon obtained a Bachelor’s Degree from Shanghai University of Science & Technology; a Master’s Degree and a Doctoral Degree from Rensselaer Polytechnic Institute. He holds more than 40 patents and over 30 publishments.

Tom Stokes

Senior Managing Director, Evercore

Biography

Tom Stokes is a Senior Managing Director of the firm’s corporate advisory business. Mr. Stokes is focused on advising clients across the technology sector.

Prior to joining Evercore, Mr. Stokes was a Managing Director in the Investment Banking Division at Goldman, Sachs & Co., where he served as global head of Electronics and Industrial Technology Investment Banking. With over 20 years of relevant experience and over 13 years at Goldman Sachs, Mr. Stokes has extensive experience advising companies across the technology industry. In particular, he has advised on a number of the most notable recent transactions across the semiconductor, electronics and industrial tech subsectors. Clients represented by Mr. Stokes include Advanced Energy, Aeroflex, Anaren, AZ Electronic Materials, Belden, Brooks, CDW, Cobham, Corning, Dover, Edwards, Entegris, Fortive, Freescale, IBM, Lam Research, Lexmark, Macom, Molex, Keysight, Koch Industries, TE Connectivity, Samsung, Sensata, Solectron, Tokyo Electron, Universal Display, Viasystems and Vishay, among others. Mr. Stokes received his BA, MA and MEng degrees (First Class) in Engineering from Cambridge University and received his MBA degree from Kellogg School of Management.

Topic

Perspectives from Wall Street

Abstract

The semiconductor and electronics industries continue to evolve at a rapid pace.

While mergers and acquisitions activity moderated as a result of COVID-19, activity has picked up pace in recent months.  The industry continues to be altered by transformational M&A, particularly as the industry regains confidence post the initial months of the COVID-19 pandemic.

We will discuss two other industry-shaping topics.

• The rise of the high growth tech SPAC IPO is enabling young companies to raise large amounts of capital.
• Escalating tensions between the US and China are having a marked influence on CEO confidence and the industry outlook.

These are some of the topics that Tom Stokes, Senior Managing Director of Evercore, will discuss in his presentation.   Evercore is a leading independent global investment bank, founded in 1995 with approximately 1,950 employees, and has advised on over $3 trillion of announced M&A transactions.  Tom has 20+ years of relevant experience and joined Evercore after a 13+ year career at Goldman, Sachs & Co.

Siva Muhandass

Vice President, Flip Chip BGA Business Unit
Amkor Technology, Inc.

Biography

Sivakumar joined Amkor in 2014 and is currently VP for the Flip Chip BGA business unit. He has served in various leadership roles as VP, global customer support & strategy and Managing Director for Amkor Singapore. Siva has more the 25 years’ experience in the global semiconductor industry. Prior to joining Amkor, he worked in management positions in the areas of Engineering, R&D and Product Marketing. Siva holds degree in mechanical engineering from University of Madras, an MS from NUS Singapore and an MBA from State University of New York.

Topic

Enabling Value Creation through Technology, Supply Chain Management & Scaling

Abstract

Flip Chip Ball Grid Array (FCBGA) is one of many complex packaging techniques among semiconductor technologies. FCBGA is driving packaging technologies to increased density and higher performance in terms of electrical and thermal requirements. Advancements in wafer technology nodes, fine pitch bumping and high-density substrate are fueling growth of FCBGA products to an inflection point. FCBGA packaging is widely used in emerging market segments such as 5G, AI, data centers, computing, automotive infotainment and autonomous driving. The requirements and time to market for these applications vary based on packaging complexity, electrical, thermal, reliability, quality and process control. Outsourced Semiconductor Assembly and Test (OSAT) companies play a pivotal role in creating value by providing engineering innovation, developing a sustainable supply chain of materials and investing in scalable manufacturing to enable and deliver these products.

This presentation will discuss the trends and challenges of the FCBGA ecosystem and the three value creation roles OSAT’s play.

Weidong Liu / 刘卫东

Technical and Marketing Director / 技术市场中心总监
Huatian / 华天科技

Biography

Graduating from Xidian University, Wade Liu has been engaged in semiconductor packaging for 12 years. He is the technical marketing director of HT-Tech, before that, he worked for Statschipac . with rich experience in advanced packaging design, simulation and assembly process. He leads the establishment and mass production of HT FC line. And develop the RF , MEMS and memory etc. products.

Topic

Advanced SiP Package Trends

Wilmer Zhou

Semiconductor Principal Consultant,
Omdia

Biography

Wilmer Zhou is a semiconductor principal consult and analysts for APAC industrial semiconductors, Industrial IOT, semiconductor manufacturing and semiconductor equipment. He is conducting extensive research in areas of processors, power semiconductors and passive components.
Wilmer was previously a product marketing manager in the semiconductor IDM company and fabless IC design house for Vishay and Auvitek. He was also an electronics engineer in the leading electronics ODM.

Wilmer has a Bachelor of engineering degree in mechatronic engineering from the University of Electronic Science & Technology of China. He also holds an M.B.A. from Shanghai Jiao Tong University.

Project Leader, CEA

Jean Charles Souriau

Project Leader, CEA

Biography

I am a project and scientific leader in the field of Micro-Interconnection and Packaging since more than 20 years. I currently work for the Commissariat à l’Energie Atomique in the LETI. I got my Ph.D in Physics in 1993 from the Grenoble University (FRANCE) in the field of laser materials and I joined the CEA-LETI in 1994. I am the first author of several publications and more than 10 patents in the field of wafer level packaging, micro systems technologies and 3D integration. I am an IEEE senior member and president of the IEEE Electronic Packaging Society French Chapter.

Topic

Overview of Leti’s advanced heterogeneous integration for SiP

Abstract

System integration, performance, cost and enhanced product functionality form the major driving force behind contemporary innovations in packaging. The need for miniaturization has led to new architectures, which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of heterogeneous System in Package (SIP) faces two critical issues: the management of components from different sources and the cost of individual operations necessary to complete the package. The objective of the talk will be to present an overview of recent developments of the CEA, Leti on advanced heterogeneous integration for SiP.

Wallace Cai / 蔡骅

General Manager / 中国区总经理
CNW-China / 上海轲锐奈沃国际货运代理有限公司

Biography

Wallace joined CNW in 2016 with more than 20 years of experience in international logistics which he gained after completing a Master’s degree in International Transportation Management. He is very familiar with import and export channels and aspects of logistics in China. Wallace is a real ‘people person’ with very strong communication skills.

蔡骅先生于2016年加入CNW，他在国际物流领域拥有20多年的经验，并获得国际运输管理硕士学位。 他对中国的进出口渠道和物流各方面都非常熟悉。 蔡骅先生为人友善并具有很强的沟通能力。

Topic

Semiconductor Logistics Towards 2021

Ben Zhou / 周晓斌

VP/GM, China – Chemical Analysis Division & Material and Structural Division / 副总裁兼总经理 中国区化学分析与材料和结构分析业务
Thermo Fisher / 赛默飞世尔科技

Biography

Ben Zhou has more than 20 years of commercial experience in China and APAC region, and 3 years of VP/GM of a global business. Currently, Ben Zhou hold VP/GM role for both Chemical Analysis Division (CAD) & Material and Structural Division (MSD) China commercial operation.

CAD has three businesses: Environmental and Process Monitoring (EPM), Mineral and Material (M&M) and Field Security Instrument (FSI). MSD has four businesses: Material Science (MS), Life Science (LS), Spectroscopy (SPEC) and Semiconductor (Semi). As VP/GM, Ben has responsibility to lead these business commercial teams, together with across function support, drives development and execution of a strategic plan to generate profitable growth materially in excess of market rates.

Ben joined Thermo Fisher Scientific in 2003 and served in a variety of management roles through his 17 years career in the company, including Air Quality Instrument (AQI) China Business Development Specialist, Environmental Instrument Division (EID) China Business Development Manager, Radiation Monitoring and Security Instrument China Commercial Manager, AQI China Commercial Manager, EID China Commercial Director, EPM APAC Sr. Commercial Director, EPM VP/GM, and most recently VP/GM for both CAD and MSD China commercial, .

Ben obtained his Bachelor degree from Tsinghua University in automotive engineering and Master degree in electrical engineering from North Carolina State University in 1993.

Topic

Advanced Workflows for Accelerating Time-to-Market and Yield Learning

Abstract

As China emerges as leaders in advanced logic and memory fabrication and advanced chip design, the need for tools that accelerate yield learning and deliver great ROI in terms of Time-to-Market and automation become increasingly relevant. Thermo Fisher will talk about our leading analysis workflows to achieve fastest time to ramp for critical processes and designs.

Jennifer Zhao

GM & EVP for Advanced Optical Sensors Division, ams

Biography

Jennifer Zhao joined ams as EVP and GM for Advanced Optical Sensors Division in 2017. She served as SVP, Global Sales and Marketing at Nexperia and held multiple management positions at NXP Semiconductors and Tyco International before that. Jennifer has managed various businesses including System Management, Logic and Microcontrollers and worked with leading OEM’s worldwide in Mobile and Consumer, Automotive and Industrial segments. Currently Jennifer manages a global team with R&D, Operations, Marketing and Application resources in US, Europe, Greater Chinaand South East Asia.

Michael Wu / 吴晓东

Senior Vice President, Global Sales and Marketing / 全球销售及市场高级副总
OmniVision Technologies / 豪威科技

Biography

With almost 29 years in the semiconductor industry, Michael Wu joined OmniVision in January 2018 and has worked at Motorola, Freescale, Xilinx, Tilera, Lantiq, and most recently at Marvell Semiconductor as VP Sales and Country Manager (China). Previously he has held a variety of positions in Product Test Engineering, Regional Sales and Business Development. Having worked and lived in mainland China, Hong Kong, USA, Philippines and Malaysia, he has built business successes with end customers in the areas of mobile phone chipset, wireline and wireless networking infrastructure, IoT, storage, DSL/PON gateway, surveillance, network security, and cloud/data center. Michael’s keen understanding of technology and market opportunities and his unparalleled ability to lead and motivate teams, drive transformation and fast response to market transitions and increase customer relevance and growth. Michael holds BSEE and MSEE degrees from Tianjin University and EMBA degrees from the Kellogg School of Management at Northwestern University and from Fudan University.

全球销售及市场高级副总

吴晓东于2018年1月加入豪威科技，被任命为全球销售高级副总裁， 并于2018年6月任职全球销售及市场高级副总裁。吴晓东从事半导体行业近29年，曾就职于摩托罗拉、飞思卡尔半导体、赛灵思、Tilera、Lantiq等公司，担任过产品测试工程师、区域销售及业务发展等多个技术及管理职位。在加入豪威科技之前，吴先生曾是Marvell美满科技半导体公司高级销售总裁兼中国区总经理。 他曾在中国大陆、香港、美国、菲律宾以及马来西亚工作及生活，与手机芯片模组、有线及无限网络基础设施、IoT、存储、DSL/PON家庭网关、安防、网络安全、云端/数据中心等各大领域市场的终端客户都建立了成熟的业务关系。他对市场及科技敏锐的把握，以及领导启发团队的能力，都使其在加速推动公司的市场转型及变革，增加客户关联及增长上取得巨大成效。吴晓东毕业于天津大学，拥有电气工程学士及硕士学位，并且拥有西北大学凯洛管理学院以及复旦大学EMBA学位。

Topic

Explore The World, Sensing Infinity / 探索世界，感知无限

Abstract

We are in the world moving from traditional computing era to AI and further to intuitive era. CMOS sensor as the advanced sensing tip, is around us and improving our daily life anywhere and anytime. OmniVision Group enables sensing possibilities with intelligent and reliable solutions!

我们的世界正在从传统的计算时代快速地进入人工智能时代，未来进入感知时代。 图像传感器作为先进的感知末梢，无处不在的伴随并改善着我们的生活。豪威集团提供智能可靠的图像解决方案，使一切皆能感知！

M. Jürgen Wolf

Fraunhofer IZM, All Silicon System Integration Dresden-ASSID

Biography

M. Juergen Wolf received a M.S. degree in Electrical Engineering from the Technical University Chemnitz. After gaining fundamental experience in the industry for several years, he joined the faculty Microperipheric Technologies at the Technical University Berlin. Here, he was mainly involved in the development of wafer level packaging processes, the development of flip chip multi-chip modules, RF modules and high density pixel detector modules.

In 1994 M. Juergen Wolf changed to Fraunhofer Institute for Reliability and Microintegration IZM Berlin and worked as a group & project manager in the department HDI&WLP in the field of wafer level packaging and system in package (SiP). He was especially responsible for the development, coordination and implementation of new technologies for wafer level packaging and system integration.

From 2000 until 2010 he additionally took over the position of personal assistant for the director of Fraunhofer IZM – Prof. Dr.-Ing. Dr.-Ing. E.h. Herbert Reichl. Starting in 2009, he was coordinating and planning and realization of the new center – All Silicon System Integration Dresden – ASSID of Fraunhofer IZM. Under his leadership a full industrial compatible process line for Wafer level Packaging and 3D integration was established. Since 2011, he is head of the department “Wafer Level System Integration” and also continued managing the center ASSID featuring a 200/300 mm 3D wafer level integration line.

M.J. Wolf is actively involved in a number of research projects on national, European and international level. M. Juergen Wolf is a member of IEEE and SMTA and among others, a longstanding member and European representative in different technical international packaging groups e.g. formally TWG of Assembly & Packaging of the International Roadmap of Semiconductors (ITRS) and now the Heterogeneous Integration Roadmap (HIR) and the Jisso International Council (JIC) where he is actively contributing to the strategy and packaging roadmap development.

Since 2016 Wolf is a member of the advisory board of 3D Incites (https://www.3dincites.com/about-us/advisory-board/). Wolf is one of the initiators and co-chair of the Fraunhofer Cluster 3D Integration which was established in 2013 and comprises 5 Fraunhofer institutes. He has also initiated the annual 3D European Summit Conference where he is a member of the steering committee.

He has authored and co-authored numerous scientific papers presentations and reports in the field of microelectronic packaging and holds a number of patents.

Topic

Microelectronic Packaging goes Heterogeneous Integration

Abstract

Main relevance of heterogeneous system integration is to address the needs of complex functionality cost targets and time to market for products in the application areas such as Industry 4.0, Artificial Intelligence (AI), Internet of Things (IoT), Cyber Physical Systems (CPS), , Ambient Assisted Living (AAL) autonomous driving etc..

Today‘s system integration technologies are driven by System in Package (SiPs) approaches. New technologies are emerging to address the requirements regarding enhanced performance, miniaturization, high speed wireless data transmission, power delivery and multi-device integration.

In this context, heterogeneous integration takes place on wafer level and on board/substrate level as well. Heterogeneous Integration refers to the integration of separately manufactured components and devices into a higher packaging level. Beside the development of new processes and the implementation of new materials heterogeneous integration requires an overall approach which includes design and reliability tasks. The talk will focus on some aspects for the realization of Heterogeneous Wafer Level -SiPs.

Jan Vardaman

President & Founder, TechSearch International, Inc

Biography

E. Jan Vardamanis president and founder of TechSearch International, Inc., which has provided market research and technology trend analysisin semiconductor packaging since 1987.She is the co-author of How to Make IC Packages(by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly,and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPSand is anIEEE EPSDistinguished Lecturer.She is a member of SEMI,SMTA,IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Topic

The New Era of Heterogeneous Integration: Promises and Pitfalls

Siva Sivaram

President WD, Western Digital

Biography

Dr. Siva Sivaram is President, Technologyand Strategy,at Western Digital where he is responsible for the development of the corporate strategy and the technologies that fuel the company’s growth.

Sivaram has more than 35 years of experience in semiconductor technologiesand manufacturing. He has held executive positions at Intel, Matrix Semiconductor and at SanDisk after its acquisition of Matrix. Additionally, he was the founder and CEO of Twin Creeks Technologies, a solar panel and equipment company.

Sivaram has authored numerous technical papers and a textbook on chemical vapor deposition and holds several patents in semiconductor and solar technologies.

Sivaram serves on the board of directors of the Global Semiconductor Alliance and the US-India Business Council. He has been on the board of directors and advisedseveral start-up firms and was entrepreneur-in-residence at Crosslink Capital and XSeed Capital.

He also serves on the board of Akshaya Patra, the world’s largest NGO dedicated to feeding school children.

Sivaram received his Doctorate and Master’s degrees in Materials Science from the Rensselaer Polytechnic Institute and has been nominated to its Board of Trustees. Additionally, he is a Distinguished Alumnus of the National Institute of Technology, Tiruchi, India, where he received his bachelor’s degree in Mechanical Engineering.

Guoqiang Shen / 沈国强

Engineering Director / 工程总监
JCET / 星科金朋半导体（江阴） 有限公司

Biography

Mr. Shen holds B.S. degree in Mechanical design and manufacturing from He Nan University of Science and Technology. He has more than 23 years of working experience in the semiconductor industry since 1996. He has been working on end-to-end development, technology transfer, NPI & high volume production in FBGA, QFN, QFP, MEMS and Memory package in STATS ChipPAC. He is currently in charge of JSCC WB group R&D center and engineering team, and focusing on core customer technology support in WB advanced assembly technology and product development. He holds over 3 US patent in the field of advanced packaging.

Topic

Advanced Assembly Technology for Memory Product

Abstract

5G, AI and IoT systems are going to increase amount of data generation up 163 ZB by 2023 systems and this amount of data generation will require more storage capacity including solid-state nonvolatile flash memory and also require higher data processing capacity for double data rate static memory. Those memory trend requires high density silicon in a memory package for static miniaturization and higher memory storage. And also different type of applications require different types of multi-chip memory package with multiple functions. Thus, the current chip memory packaging requires the optimized structure and material selection, and this memory session will show some advanced memory packaging technologies, challenges and solutions done by JCET group.

Wenhao Sha / 沙文灏

Chief Data Scientist & Technical Expert at Group Strategy Committee and Dean of Institute of Intelligent Society, Shenlan Academy of Sciences / 首席数据科学家 集团战略委员会战略技术专家 深兰科学院智能社会研究院 院长
DeepBlue / 深兰科技

Biography

Dean Sha has an extensive experience in the field of Artificial Intelligence and has published many papers on best practices for implementation including “Theory of Digital Strategy”, “AI Implementation Methodology” and “Methodology for Large Scale IoT System”. He has also participated in the design and planning for the 14th 5-year industry development plan for the Shanghai city. Dean Sha has served as the Head of Business for China at AtoS, , Europe’s largest consulting firm, He was also global head of the renowned company CDI, a top 3 strategy consulting firms in Japan. He possessed more than 33 years of industry experience, with 18 years in major projects (10,000 man-months) in Japan. He has served many major multi-national corporate clients such as Toyota and Hitachi for project implementation and was responsible for Business development and production management for Toyota Group at Japan headquarter, He has served as expert for the Japanese Ministry of Foreign Affairs (JICA) and also, as member of the Information System Committee of the Japanese Electrical Society. He has also published two information systems monographs and teaching materials in Japan. In summary, having full responsibility for many mission critical projects, he has a wealth of diverse experience including enterprise strategy, management, business processes, blueprint design, business communication and system design and implementation. With his meticulous and reliable project management, he has achieved outstanding outcome with more than 95% of project success rate and has received great recognition in the industry in China and Japan.

Topic

DeepBlue Technology Explainable Artificial Intelligence (XAI) Technology

Abstract

As AI accelerates the pace of enterprise innovation, it has transformed business automation from simple tasks to become a very powerful tool for Human-Machine Collaboration. As a result, AI is no longer viewed as a simple technical tool but rather, has triggered holistic transformation for the entire organization. In the future, companies will place human-machine collaboration as their core strategy and will embrace these technology tools and methodologies for business improvement by enabling better understanding and interactions between humans and machines. AI technologies such as Natural language processing and understanding will certainly enable machines with enhanced capabilities to understand written and spoken texts. Advances in Virtual Reality and Computer Vision will also help machines to accurately recognize the physical environment around people. Explainable AI (XAI) will thus become a critical component to close the loop to allow human to understand how machines make decisions. With Human-Machine Collaboration model, enterprise will be able and will need to completely restructure and transform their business including organization structure and design, product design, employee recruitment and training etc.

Donghui Lu / 卢东晖

Senior Director of NAND Process Development
Intel Dalian / 英特尔

Biography

Currently Donghui Lu is Senior Director of Process Development for NSG (Non-Volatile Memory Solutions Group) at Intel, managing Process Development organization (based in Dalian, China) to develop future generations of 3D NAND process technologies. He is also Senior Director of Technology and Strategy Office for Intel Dalian, responsible for strategic initiatives and business planning.

Donghui joined Intel Fab D2 in Santa Clara, California, in 2000, where he worked on many generations of technology development on logic/flash memory/communication devices. He was technical gatekeeper as Integration Manager during Intel Dalian’s 65nm logic greenfield startup in 2010. Since 2015 Donghui was Intel Transfer Manager transferring 3 generations of 3D NAND technologies from Micron. In 2017 Donghui was Program Director building the biggest single cleanroom for Intel in Dalian in record 9 months at world class cost. Since 2018 Donghui started and co-led Dalian technology development teams, and successfully delivered Intel’s first independently developed 144-tier 3D NAND technology in 2020.

Donghui received Bachelor’s degree from Tsinghua University in Beijing in 1994, and PhD from The Ohio State University in Columbus, Ohio in 2000, both in Materials Science and Engineering. He also received joint Executive MBA degrees from University of California at Berkeley, and Columbia University in New York, in 2007.

Topic

Pushing the Frontier: Intel 3D NAND Technology

Santosh Kumar

Director & Principal Analyt, YOLE Development

Biography

Santosh Kumar is currently working as Director & Principal Analystat Yole Développement. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

He received the bachelor and master’s degree in engineeringfrom the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advancedmicroelectronics packaging.

Gaurav Kaul

Senior Architect, HPE

Biography

Gaurav Kaul is an AI/Big Data Consulting Architect in HPE. As part of the HPE Pointnext Services team, Gaurav works with customers in their ArtificiaI Intelligence and Machine Learning transformation projects from infrastructure to application level. This involves architecting solutions for both hybrid and edge deployments using HPE hardware and software solutions, including HPE BlueData. Previous to HPE, Gaurav has worked in Amazon Web Services, Intel and IBM. He lives in London, UK and works with HPE customers across EMEA.

Farhat Jahangir

VP of Manufacturing & GM of East Fishkill 300mm-Fab, ON Semiconductor

Biography

Farhat joined ON Semiconductor through Quantenna Communication acquisition in March 2019 where he was serving as SVP of Manufacturing, Operations & Quality for six plus years. Farhat played a pivotal role in making Quantenna successful through manufacturing structure optimization, cost reductions, quality & margins improvement thus enabling Quantenna’s successful IPO in October 2016. Farhat’s experience includes global manufacturing operations, supplier management, building 3rd party partnerships, and the assurance of quality & reliability processes.

Farhat has over 20 years of successful experience in global manufacturing operations, quality & reliability functions of the Integrated Circuits & System Products. Prior to joining ON Semi/Quantenna Communications, he headed semiconductor manufacturing operations and quality functions at Synerchip Corporation (acquired by Silicon Image) & SiTime (a MEMS based timing solution company). Farhat has expertise in building and restructuring company’s lower margin product lines to higher margins, enabling market penetration and corporate margins growth. Farhat also held various engineering and management positions in the areas of semiconductor manufacturing in companies like Texas Instruments, Cypress Semiconductor, Silicon Image & IDT.

Farhat holds a Master of Science degree in Electrical Engineering from University of Arkansas at Fayetteville.

Topic

Transformation of Connectivity

Dr. Karl Fuchs

Vice President, Innovation & Technology China, Continental

Biography

Dr. Karl Fuchs is vice president, Innovation & Technology China, with a primary focus on intelligent infrastructure, intelligent connected vehicle, autonomous driving, high-performance computing and driving software and system engineering excellence. Karl joined Continental in 2008 and had leading positions in engineering and was a vice president, Infotainment & Connectivity Quality in Singapore and Corporate Quality in China. He has a many years’ experience in both software engineering and software quality. Karl is a Continental internal lecturer in large-scale software engineering covering particularly software complexity, software quality and defect management, defect prediction models, software testing and software development productivity. Prior to Continental, Karl worked from 1994 – 2007 with Siemens Mobile Radio Networks Infrastructure in Munich and Ulm. As vice president R&D he was responsible for the worldwide development of the operation and maintenance software system of the radio access networks GERAN, UTRAN, and BWA as well as for the mass date configuration management of radio and transport databases for radio/core network elements. Karl has a master’s degree and a summa cum laude Ph.D. degree in computer science from Technical University of Munich. After university, Karl joined for 3 years the central research and advanced development organization of Siemens where he worked on automatic test pattern generation techniques for different failure models, synthesis for testability in cooperation with university of Berkeley, and the application of build-in-self-test methods in VLSI circuits. Dr. Fuchs did 17 publications, mainly IEEE, during his research work at the university of Munich and the research center of Siemens.

Topic

Vehicle EE Architecture: centralized High-Performance Computer and core enabler Software

Abstract

The intelligent connected vehicle (ICV) continuously drives the change in E/E vehicle architecture. Main drivers are an increasing number of equipped sensors, an enormously required communication bandwidth going along with enormous computing power capability, steadily increasing external vehicle communication (e.g. 5G, V2X), and finally global time synchronization. The evolution of the E/E vehicle architecture towards a centralized, zonal E/E setup is described. High Performance Computers (HPCs) will become the core of vehicle electronics and will host most of the software. In addition, zonal architectures bear significant savings in length of the wiring harness. There are many challenges in the non-straight forward transition from today’s to future E/E architecture due to both hardware and software legacy. Software excellence will become a key-enabler to master highest complexity. Key areas to be addressed are design for reuse, higher abstraction levels to intellectually understand a complex system, agility along with model/design execution and a high professionalism in software development

Michael Ehinger

Vice President, TRUMPF Huettinger Elektronik GmbH

Biography

Michael Ehinger is the vice president and has been with TRUMPF Hüttinger for 15 years. He was responsible for sales, service, and marketing during these years. Before entering the company, Michael took the position of the division manager in SICK AG and was the product manager in Draeger AG between 1990 and 1992. Michael studied in the University of Applied Science in 1986 and obtained his second degree from Brunel University in London.

Topic

Innovative Process Power Solutions for Semiconductor Industry

Abstract

TRUMPF´s innovative process power solutions help tool makers and chip makers to overcome daily challenges like wafer to wafer uniformity, controllability of critical dimensions as well as reducing operational cost over the lifetime. Beside the hardware, TRUMPF is also offering engineering expertise for modelling and layout of thermal heating applications used e.g. in SiC crystal growth systems.

Leo Chen / 陈颂

Partner，Semiconductor Industry Leader of Deloitte China / 合伙人，德勤中国半导体行业领导人
Deloitte / 德勤华永会计师事务所

Biography

Mr. Chen has more than 20 years of professional experience and has been a partner at Deloitte since 2012. He worked in Deloitte New York Office from 2003 to 2005. He is one of our audit partners in Shanghai focusing on serving TMT industry clients, especially semiconductor industry

Mr. Chen is Member of Chinese Institution of Certified Public Accountants (CICPA). Leo also is the Member of American Institution of Certified Public Accountants (AICPA).

Mr. Chen’s major clients include: Spreadtrum, Verisilicon, Ultra Clean, Monolithic Power System、Wangsu Technology、Yongda Group.

§陈颂先生是德勤华永会计师事务所的审计合伙人。陈先生于1998年加入德勤上海，期间于2003年到2005年工作于德勤纽约办公室。

§陈先生专职于国内公司的中国及海外资本市场上市业务、上市公司以及跨国公司的审计以及咨询服务，拥有半导体、互联网通讯、零售业以及制造等多个行业的从业经验。陈先生的主要客户包括展讯通信、芯源股份、超林半导体、成都芯源、网宿科技、永达汽车等。

陈先生为中国注册会计师及美国注册会计师。

Topic

Rise of the “Big-4” – The semiconductor industry in Asia Pacific / 亚太四大半导体市场的崛起

Abstract

Driven by government support, vast market and increasing R&D spending, China, Japan, South Korea and Taiwan together have become the “Big 4” semiconductor players in Asia Pacific. The demand for optoelectronic products increases, as well as the maturity of many disruptive technologies, including AI, big data and 5G, will drive the growth of the semiconductor market. “Multi-markets” emerges after COVID-19, supply chain network resilience is the key.

在政府支持、巨大市场体量以及研发投入增加等众多因素的推动下，中国大陆、日本、韩国和中国台湾成为亚太地区四大半导体市场。

亚太四大半导体市场正于全球加速崛起，而5G、人工智能、大数据将成为推动市场需求的主要因素。随着半导体行业在后疫情时代逐渐形成“多极市场”，增强供应链韧性将会是成功的关键。

CL Cao / 曹持论

President & Country Manager / 董事&中国区总裁
Amkor Technology China / 安靠封装测试（上海）有限公司

Biography

CL (ChiLun) Cao joined Amkor in 2001 and is currently President, Board Director of Amkor Technology China. Prior to assuming his current role, CL served as VP of Amkor Technology China. Since joining Amkor, he has held various key management positions in engineering and operations. CL has 25 years of experience in the semiconductor industry, including positions with Hyundai Electronics and STATSChipPAC. He serves as Vice President of Shanghai Integrated Circuit Industry Association and Executive Director of Shanghai Association of Foreign Investment. CL holds a BS degree in Thermal Engineering from Shanghai University of Engineering Science and MBA from The University of Texas at Arlington.

曹持论于2001年安靠上海成立初期加入公司，先后担任技术、生产等多个重要岗位，在接任总裁之前担任安靠上海厂长一职，参与并见证了安靠上海从设立到发展壮大的全过程。他有着25年的集成电路封测产业技术和管理经验，是中国大陆首批掌握中高端集成电路封装技术的先行者。加入安靠之前，曹持论曾在Hyundai Electronics，STATSChipPAC等公司工作。曹持论拥有上海工程技术大学热能工程学士学位以及美国德克萨斯大学阿灵顿分校EMBA学位。

Topic

Addressing Packaging Challenges for Growing Memory Market / 如何应对不断发展的存储器市场所面临的封装挑战

Abstract

Key market applications such as 5G, datacenters and AI are driving an insatiable demand for system memory and storage. As technology nodes scale down and density of memory goes up, it presents key challenges to provide effective packaging and test solutions. In this presentation, we will address some of the key issues and provide recommendations that will address the ever evolving memory packaging and test market.

5G、数据中心和人工智能等这些重要的应用市场正在推动对系统内存和存储的巨大需求。随着晶圆制造技术节点的进化和存储密度的增加，封装和测试解决方案也面临着关键挑战。在这次介绍中，我们将就一些关键问题进行讨论并提供建议，希望给解决不断发展的存储器封装和测试市场的需求提供帮助意见。

Dr. Karl Breidenbach

Senior Director Production Partner Procurement, Infineon

Biography

Dr. Karl Breidenbach is a Senior Director at Infineon Technologies AG’s procurement production partner organization. Dr. Breidenbach is focused on leveraging outsourcing opportunities with leading silicon foundries and outsourced semiconductor manufacturing and test (OSAT) companies across logic and power technologies.

Prior to joining Infineon, Dr. Breidenbach was a senior consultant in the Strategy and Transformation Division at IBM, where he consulted clients in automotive, electronics and the process industry on supply management optimization. With over 15 years of relevant experience, Dr. Breidenbach has extensive knowledge in semiconductor technology outsourcing across the entire value chain including R&D, software, factory integration and manufacturing. In particular, he was instrumental in leading a global corporate carve out to Lenovo in Asia, Europe and the US.

Dr. Breidenbach holds a PhD from Bundeswehr University Munich, Master of Science (First Class) from Dublin City University and NEOMA Business School in Supply Chain Management, and a BA from Aston University Birmingham and Baden-Wuerttemberg Cooperative State University Stuttgart in Information Technology and International Business Management.

Topic

Status quo Semiconductor Outsourcing Supply Chain 2020: Where is it now and what are the challenges in the future?

Abstract

The presentation looks at the state of the global semiconductor outsourcing supply chain and investigates the future challenges that companies like Integrated Device Manufacturers and fabless companies face together with their key external partners across the ecosystem in R&D, external frontend manufacturing and outsourced assembly and test.

Ruurd Boomsma

CTO, Besi

Biography

Ruurd Boomsma received a Master Degree with focus on Semiconductor Physics and High Vacuum Technology, from the State University of Groningen, the Netherlands. He started working in the semiconductor industry in 1984 at ASM in Bilthoven, the Netherlands, in front end equipment including Epi, Diffusion, PECVD Implant and Litho and was also involved in the sales of the first steppers from ASML (at that time part of ASM). Then moved to MRC, a USA based company for PVD and Etch equipment and later he became responsible for the Unaxis (Oerlikon) Materials and Display Divisions. He is now over 10 years active at Besi. Initially involved in technology assessment, supply chain optimization followed by holding the responsibility for the Plating product group and later full responsibility for the Die Attach product group. He is now Besi’s Chief Technology Officer and also responsible for strategic supply chain management and overall quality.

Topic

Opportunities in next generation advanced bonding and molding technology

Abstract

Advanced packaging is becoming a key enabler for next generation semiconductor devices. There is a clear trend towards larger die dimensions, more dense contact schemes as well as more variation in device structures. This has major impact on the required equipment capabilities in the fields of accuracy, die size handling, cleanliness, productivity and flexibility. This presentation will highlight some of the new opportunities in bonding and contact technology including Thermal Compression Bonding and Direct Cu-to-C hybrid bonding as well covering advancements in molding technology for advanced packaging.

Sébastien Bernard / 白胜天

Asia-Pacific Strategic Partnerships & Business Intelligence Director / 战略合作与商业情报总监 亚太区
ST China / 意法半导体

Biography

Sébastien Bernard is Director, Strategic Partnerships and Business Intelligence in STMicroelectronics’ Asia-Pacific Region and has held this position since 2019.

Sébastien joined STMicroelectronics in 2000 and has held various management positions in Corporate Strategy, Strategic Partnerships, Sales and Marketing, and Business Development. In the past 20 years working for ST in China, he has contributed to several large-scale industrial projects focused on the Company’s fab and assembly plants. Sébastien has established partnerships with local companies to support the Chinese semiconductor industry and has developed new businesses for ST. In 2013, he was appointed Counsellor to the French Government on foreign trade matters.

Sébastien Bernard was born in France in 1970 and graduated with a Master’s degree in Semiconductor Devices Technology from Ecole Centrale de Lyon in France, after conducting a research work on semiconductor material at Tsinghua University, Beijing, in 1994.

Sébastien Bernard于2019年至今任意法半导体亚太区战略合作总监。

Sébastien于2000年加入意法半导体，先后在公司战略、战略合作、市场营销和业务拓展等部门担任过多个管理职务。在过去20年来，他在意法半导体中国分公司工作，为多个与晶圆厂和封装厂相关的大型工业项目落地做出了贡献。Sébastien与国内企业建立了合作关系，支持中国半导体产业发展，并为意法半导体开发了新的业务。2013年，他被任命为法国政府对外贸易事务顾问。

Sébastien Bernard 于1970年出生于法国，获法国里昂中央大学半导体器件技术硕士学位，他曾于1994年在清华大学从事半导体材料研究工作。

Topic

The Future of Power

Andy Hsieh / 谢文元

Senior Director of FAB PE / 工艺高级总监
Innoscience (Zhuhai) Technology Co., Ltd / 英诺赛科（珠海）科技有限公司

Biography

Has 12 years top fab process experience of semiconductor, especially in GaN-on-Si process. Focus on GaN-on-Si technology not only in R&D but also production. Be responsible for all 8” GaN-on-Si process development and maintenance in Innoscience. Look forward to bringing GaN-on-Si technology to the industrialization and leading this technology in the world.

有超过12年最顶尖半导体工厂工艺经验，特别是在硅基氮化镓相关部份。专注于硅基氮化镓技术的研发与量产。目前在英诺赛科管理所有八英吋硅基氮化镓工艺的研发及维护，期待带来硅基氮化镓的产业化及于世界也能引领硅基氮化镓工艺技术。

Topic

Progress of 8 inch GaN-on-Si industrialization

Abstract

GaN power devices and its technology development have been attractive by lots of research groups for more than three decades. To realize high volume mass production and commercialization, GaN epitaxy on silicon (GaN-on-Si) HEMTs is proven just recently. Especially, advantages of higher production efficiency, more advanced process, better supply chain, and cost-efficient in CMOS compatible manufacturing are achievable in 8 inch GaN on Si. Applications of quick charger, lidar, and etc., and more updated industrial status will be discussed.

氮化镓功率器件及其技术发展吸引了众多研究单位投入，至今已经超过三十年。为了实现大量量产与商业化，氮化镓外延在硅上(硅基氮化镓)的高電子迁移率晶体管在近期已被验证可行。 八英吋硅基氮化镓在使用CMOS兼容工艺制造上具有明显优势，特别在高生效效率、先进的工艺技术、较佳的半导体供应链以及较低的成本方面。快充、激光雷达及更多将被产业使用的相关应用也会在此探讨。

Ramin Farjadrad

CTO/VP Networking/Automotive PHYs, Marvell Semiconductor

Biography

CT & VP of Networking/PHYs at Marvell Semiconductor, in charge of developing multi-GHz connectivity solutions for Autonomous vehicles, Hyperscale data centers, and Heterogenous system-in-package (SiP) Integration. Chairman of technical committee at Networking for Autonomous Vehicles (NAV) Alliance. Proposed signaling schemes adopted as IEEE Standard for Multi-Gbps Automotive Ethernet (802.3ch) and Enterprise Ethernet (802.3bz). Domain expertise in high-speed communication circuits & systems, signal processing/coding, optimized mixed-mode architectures. Author of 100+ granted/pending US patents. M.Sc./Ph.D. in EECS from Stanford University.

Topic

From SoC to SiP: Inter-Chiplet Connectivity Solutions for Heterogeneous Integrations

Abstract

This presentation covers the current state of Heterogeneous system-in-package (SiP) architectures and solutions to address the challenges that the semiconductor industry has been facing in recent years to keep up with the Moore’s law. It discusses how the path from SoCs to SiP Solutions helps reduce the high cost of IC development and manufacturing, and also create new possibilities, and how some of the latest inter-chiplet PHY technologies that enable this trend.

Corporate VP, GM Assembly & Test Technology Development, Intel Corporation

Babak Sabi is the Corporate Vice President and General Manager of Assembly and Test Technology Development.  Since 2009, he has been responsible for the company’s packaging assembly process, packaging materials, enabling assembly and test technology development.  Sabi joined Intel in 1984.

Prior to leading ATTD, Sabi led the Corporate Quality Network within Intel’s Technology Manufacturing Group from 2002 to 2009. He led a company-wide network of quality and reliability organizations responsible for product reliability customer satisfaction and quality business practices.

Previously,  Sabi managed technology development quality and reliability and was responsible for silicon technology certification, assembly, test, and board processes.

Sabi received his Ph.D.in solid-state electronics from Ohio State University in 1984. He has written 10 papers on reliability physics and has received 5 Intel Achievement Awards.  He currently holds 2 patents.

CTO, Huatian Group

Dr. Daquan Yu is a Distinguished Professor of Xiamen University and the CEO of Xiamen Sky Semiconductor Co., Ltd. He was the President of Research Academy of Advanced Packaging Technology of TSHT Group from 2014 to 2019. He was a professor of Institute of Microelectronics, Chinese Academy of Sciences from 2010 to 2015. He had carried out research work at Fraunhofer IZM in Germany, and Institute of Microelectronics in Singapore from 2005 to 2010. He has authored or co-authored more than 160 peer-reviewed technical publications. He holds more than 40 patents. He is an IEEE senior member since 2013.

EVP and GM for Advanced Optical Sensors Division, AMS AG

Jennifer Zhao joined ams AG as EVP and GM for Advanced Optical Sensors Division in 2017. She served as SVP, Global Sales and Marketing at Nexperia and held multiple management positions at NXP Semiconductors and Tyco International before that. Jennifer has managed various businesses including System Management, Logic and Microcontrollers and worked with leading OEM’s worldwide in Mobile and Consumer, Automotive and Industrial segments. Currently, Jennifer manages a global team with R&D, Operations, Marketing and Application resources in the US, Europe, Greater China, and South East Asia.

CTO & VP, Powertech Technology Inc.

1. Setup and led PTI package R&D center to develop 32 chips stacking, fine pitch FC, WL, Panel Fan out, and 3DIC TSV package.

2. Held multiple managerial positions in semiconductor companies of IC design, process, and packaging

3. Has been filed and granted 60 patents worldwide.

Senior Director, SPIL

Wang Yu-Po received Ph.D. in Mechanical Engineering from State University of New York at Binghamton, U.S.A

In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore. He has jointed SPIL since 1998 and led the R&D advanced packaging design team for leadframe, substrate and wafer form packages development.

Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has 83 patents in US.

Experience:

• 1997-1998 Gintic Institute of Manufacturing Technology, Singapore
• 1998-Present SPIL, Taiwan

EVP Head of Substrate Solution Business Unit, Samsung

Graduated from Stevens Institute of Technology with a Ph.D. in Material Science & Engineering

• 17.04 ~ Now   GM & EVP of Substrate Solution Business Unit in Samsung Electro-Mechanics Co., Ltd.
• 14.12 ~ ‘17.03  Head & SVP of Global Technology Center in Samsung Electro-Mechanics Co., Ltd.
• 12.12 ~ ‘14.11  GM & Head of Manufacturing Technology Center of System LSI Business Unit in Samsung Electronics Co., Ltd.
• 10.08 ~ ‘12.11  GM & SVP of Texas Austin FAB of System LSI Business Unit in Samsung Electronics Co., Ltd.
• 07.01 ~ ‘10.07  VP of Manufacturing Technology Center of System LSI Business Unit in Samsung Electronics Co., Ltd.

VP Advanced Packaging, Fraunhofer IZM-ASSID

M. Juergen Wolf received a M.S. degree in Electrical Engineering from the Technical University Chemnitz. After gaining fundamental experience in the industry for several years, he joined the faculty Microperipheric Technologies at the Technical University Berlin. Here, he was mainly involved in the development of wafer level packaging processes, the development of flip chip multi-chip modules, RF modules and high density pixel detector modules. In 1994 M. Juergen Wolf changed to Fraunhofer Institute for Reliability and Microintegration IZM Berlin and worked as a group & project manager in the department HDI&WLP in the field of wafer level packaging and system in package (SiP). He was especially responsible for the development, coordination and implementation of new technologies for wafer level packaging and system integration. From 2000 until 2010 he additionally took over the position of personal assistant for the director of Fraunhofer IZM – Prof. Dr.-Ing. Dr.-Ing. E.h. Herbert Reichl. Starting in 2009, he was coordinating and planning and realization of the new center – All Silicon System Integration Dresden – ASSID of Fraunhofer IZM. Under his leadership a full industrial compatible process line for Wafer level Packaging and 3D integration was established. Since 2011, he is head of the department “Wafer Level System Integration” and also continued managing the center ASSID featuring a 200/300 mm 3D wafer level integration line. M.J. Wolf is actively involved in a number of research projects on national, European and international level. M. Juergen Wolf is a member of IEEE and SMTA and among others, a longstanding member and European representative in different technical international packaging groups e.g. formally TWG of Assembly & Packaging of the International Roadmap of Semiconductors (ITRS) and now the Heterogeneous Integration Roadmap (HIR) and the Jisso International Council (JIC) where he is actively contributing to the strategy and packaging roadmap development. Since 2016 Wolf is a member of the advisory board of 3D Incites (https://www.3dincites.com/about-us/advisory-board/). Wolf is one of the initiators and co-chair of the Fraunhofer Cluster 3D Integration which was established in 2013 and comprises 5 Fraunhofer institutes. He has also initiated the annual 3D European Summit Conference where he is a member of the steering committee. He has authored and co-authored numerous scientific papers presentations and reports in the field of microelectronic packaging and holds a number of patents.

Technical Director, NCAP

Dr. Yao joined NCAP China as a technical director in June 2017. He has been responsible for extending technical capability in FOWLP and establishing volume production lines dedicated to FOWLP. Jiangsu CAS Microelectronics Integration Technology Co Ltd, CASMEIT, was founded in Xuzhou city, Jiangsu province in March 2018, where Dr. Yao currently serves as CEO. Prior to this role, Dr. Yao serves as a senior member of technical staff and metal CVD core team leader in Applied Materials Inc., Santa Clara, California, USA. He had worked for the company for over 21 years in various roles, including the development of various IC manufacturing processes and equipment.

Partner, Deloitte

Lilly is a seasoned digital innovation executive with over 30 years of experience advising both Fortune 500 and emerging technology companies doing business globally.  Lilly’s career reflects a demonstrated track record in driving innovation, leading successful large-scale digital transformation initiatives in complex, global business environment, and executing strategic alliances in the technology ecosystem.  She brings deep expertise in strategy and execution of major M&A deals and post-merger integration synergy capture as well as the deployment of cloud, industrial IoT, and Industry 4.0 solutions.  Lilly brings a broad set of industry experiences, including semiconductor, automotive, ecommerce, and manufacturing in both the US and China.

Lilly is responsible for the relationships and client engagements for some of Deloitte’s largest global clients and works cross-border in China, Japan, Brazil, India, and EU countries.  Lilly led a team to help a $170B manufacturing company to develop its acquisition strategy, execute the transaction, and obtain post-merger synergy in a successful M&A deal valued near $900M.  Lilly has been working closely with digital platform companies to develop technology-enabled transformation solutions for enterprises in new retail, automotive, FinTech and smart cities.

Lilly has led numerous strategic initiatives for Deloitte and is recognized for her commitment to nurturing and promoting women leadership and inclusion in technology companies.  She is an advisor for the Women in Engineering initiative sponsored by major universities in Silicon Valley and has led Deloitte’s Chinese Service Group, Women’s Initiative (WIN), Client Leader Development program and is nationally recognized as a firm expert for the semiconductor industry.   She also served on the nominating committee for Deloitte’s Board of Directors.

Lilly started her career in the semiconductor industry, where she spent 10 years as a design engineer, including the first 32-bit microprocessor.  She held increasing responsibility to include strategic planning and technology transfer at Xerox Palo Alto Research Center.  Lilly was one of the founders of Pictron, which provides video search software for Fortune 500 companies.  Lilly was responsible for all aspects of the business including fundraising, strategic partnership, business development.  Lilly also interned at the venture capital firm: TA Associates in Boston to identify investment opportunities.

Lilly is the co-chair of China Committee of Bay Area Council in California, and she served as the global chair of MJ Science and Technology Association as well as on the advisory board of UC Berkeley Extension Program.  Lilly is a frequent speaker at industry events, including the Hamburg Summit, Wharton Business School, University of Berkeley, Stanford University, as well as Chinese TV news. Lilly was also selected as one of the most influential women by the San Francisco Business Times.  Lilly is fluent in Mandarin Chinese.

Lilly received her bachelor and master degrees in Electrical Engineering from the University of Southern California.  She received her master degree in Engineering Management & Industrial Engineering from Stanford University and an M.B.A. from Harvard Business School.

SVP, Manufacturing & Quality, Quantenna

Farhat Jahangir joined Quantenna in 2013 and is Senior Vice President of Manufacturing & Quality. He brings over 20 years of success in global manufacturing operations, product engineering, quality and reliability functions of semiconductor and system products. Prior to joining Quantenna, Mr. Jahangir served as head of Operations and Quality at Synerchip / MultiMedia Crossing (IP later acquired by Silicon Image Inc.) where he oversaw high-speed, mixed-signal IC and system products from concept to end-of-life. Previously, he was the director of Operations at SiTime Corporation (a MEMS-based timing solution startup), where he was a pivotal contributor in building the company’s negative margin product line to positive – enabling market penetration and sales growth. Mr. Jahangir has held various engineering and management positions in the areas of semiconductor operations and manufacturing at such companies as Silicon Image, Texas Instruments Inc., and Cypress Semiconductor Corporation. He also has experience in global manufacturing operations, supplier management, new product development, and the assurance of quality and reliability processes. Mr. Jahangir holds a Master of Science degree in Electrical Engineering from the University of Arkansas at Fayetteville.

President & Founder, Techsearch International Inc.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC.  She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018.   She is an IMAPS Fellow.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Senior Managing Director, Evercore

Tom Stokes is a Senior Managing Director of the firm’s corporate advisory business. Mr. Stokes is focused on advising clients across the technology sector.

Prior to joining Evercore, Mr. Stokes was a Managing Director in the Investment Banking Division at Goldman, Sachs & Co., where he served as global head of Electronics and Industrial Technology Investment Banking. With over 18 years of relevant experience and over 13 years at Goldman Sachs, Mr. Stokes has extensive experience advising companies across the technology industry. In particular, he has advised on a number of the most notable recent transactions across the semiconductor, electronics and industrial tech subsectors. Clients represented by Mr. Stokes include Aeroflex, AZ Electronic Materials, Belden, Brooks, CDW, Dover, Edwards, Entegris, Freescale, IBM, Lam Research, Lexmark, Macom, Molex, Keysight, Koch Industries, TE Connectivity, Samsung, Sensata, Solectron, Tokyo Electron, Universal Display, Viasystems and Vishay, among others.

Mr. Stokes received his BA, MA and MEng degrees (First Class) in Engineering from Cambridge University and received his MBA degree from Kellogg School of Management.

CEO and Executive Vice President, Unisoc Group

Steve Chu, CEO of Unisoc Group and Executive Vice President of Unigroup, has 22 years of experience in the telecommunication, semiconductor and investment industries. Before joining Unisoc,Steve took various senior executive positions, including Vice President of Strategy and Technology at Huawei, Chief Strategy Officer at Hisilicon, Head of Huawei Innovation Incubator, Director of Wireless Business at Hisilicon, Deputy General Manager at Datang Mobile, General Manager of Wireless Research Division at Huawei and etc. Steve also led the Microelectronics Division of CAS Zhangjiang Research Center in Shanghai.

Steve is widely respected in the mobile telecommunication and microelectronics industries, as the founder of several important technologies and the owner of a number of international patents.Steve led the invention of the first commercialized wireless base station in China, and the first prototype of software radio base station inthe world. He led the development of the first mobile phone chip solution (Holly Communication’s CDMA), the first TD-SCDMA mobile phone chip solution (Datang Mobile), and the first WCDMA mobile phone chip solution (Huawei Hisilicon) in China, as well as the first set of WCDMA base station chipset in the world.

In addition to his devotion in research activities, Steve is a promotor of technology commercialization. He drove the international commercialization of the Broadband SoftwareRadioTechnology, founded the Huawei Innovation Incubator, and developed greenfield projects in high-speed railway telecommunication, e health, digital home, new energy etc.By acquiring the British start-up NEUL, Steve promoted the NB-IOT technology standard and the industry in China.

Steve has also built one of the most experienced investment team in the semiconductor industry in China. He has a successful track-record of over 10 investment and acquisitions in China, Britain, Belgium, Israel, Singapore etc. Steve was also the founding member of the Advanced Semiconductor Technology Research Center– a high profile organization established bySMIC, Huawei and Qualcomm, whose signing ceremony was witnessed by President Xi of China and King Philippe of Belgium. Steve is a member in the investment committee of the Sino IC Industry Investment Fund.

Steve graduated with a master degree from Xi‘an Jiaotong University,

VP Corporate Supply Chain & Factory Integration, Infineon

• Dipl.-Ing. (MSc) Production Technology from Technical University of Munich and PhD from Technical University of Stuttgart
• Starting 1989 applied research at Fraunhofer Institute of Production Technology and Automation for Semiconductor customers
• From 1996 on Olaf Herzog served at Advanced Micro Devices in 200/300mm waferfab startups in the roles of Director Factory Automation, Production Module Head and Director Manufacturing
• Starting 2010 Olaf Herzog took responsibility as Director Manufacturing Engineering and as Director Factory Automation for a 300mm waferfab at Globalfoundries
• In 2014 Olaf Herzog joined Infineon Technologies AG. As VP Factory Integration he is currently responsible for the factory control systems in Waferfab, Assembly and Test facilities globally

Vice President & General Manager, Broadcom Limited

Martin Weigert is the Vice President & General Manager of the Industrial Fiber Products Division which manufactures fiber products targeting the industrial, automotive and emerging markets. Martin Weigert worked for Siemens/ Osram / Infineon / Avago for over 20 years and has held various development & marketing positions in the company’s fiber optic and LED product divisions.

Martin has many years of experience in leading positions for development and marketing of optoelectronic components for the automotive and fiber optic markets. He is currently in charge of the P&L for the Industrial Fiber Product Division at Avago Technologies.

Martin studied Micro System Technology and has a technical background in MEMS, Optoelectronics and Semiconductors. He is the managing director of the Avago Technologies Fiber GmbH in Germany, Avago Technologies Fiber Austria GmbH and a member of the supervisory board at the Munich based MIC AG, an early stage investor for high tech companies.

20 years experience in Fiber Optics

• 1994 – 1997 ​Process development MEMS
• 1997 – 1998 ​Task force leader production ramp-up
• 1998 – 1999 ​Project leader optical SMD devices
• 1999 – 2000 ​Marketing Manager Automotive LED
• 2001 – 2004 ​Director Development Fiber Optics
• 2004 – 2006 ​Director Marketing POF
• 2006 – 2007 ​Director Product Line Manager (R&D+Marketing) at Infineon
• Since 2008​ General Manager Industrial Fiber Optics at Avago Technologies
• Since 2009 ​Managing Director “Avago Technologies Fiber GmbH”
• Since 2011​ Member of the supervisory board at MIC AG
• Since 2012​ Managing Director “Avago Technologies Fiber Austria GmbH”
• Since 2014 ​Vice President & General Manager – Avago

COO, Nantong Tongfu Microelectronics

Mr. Yc Lee was born in Penang, Malaysia. He has been living in Shanghai, China since 2002. He started with Intel in 1987, was given the opportunity to start-up the 1st Intel CPU assembly and test factory in Shanghai, China in 2002; followed by the 2nd CPU factory in Chengdu 2 years later.

He joined STATS ChipPAC, as the President and Managing Director for their Shanghai Plant from 2006 to 2014.

He was the Vice President, Special Assistant to Chairman in China Resources Microelectronics Limited in 2015. He was responsible for New Business Development, Company Globalization Strategies and Involved in potential merger and acquisition.

And now, Yc Lee is COO of Nantong TongFu Microelectronics Co., LTD.

Yc Lee has 32+ years of relevant experience and expertise covering Product Engineering, IC Packaging Assembly and Testing, Quality, Manufacturing Operation， Business Development, New Product Development and Introduction etc. He has lived and worked in Malaysia, U.S.A and China.

Vice President of Silicon Technology, Xilinx

Xin Wu is Vice President of Silicon Technology, XILINX INC.  He received PhD and MSc from University of California Berkeley USA and Peking University, China respectively.  Jointed Xilinx since 1993, he has worked from 0.6um till 7nm currently, more than 14 generations of technologies and products, from many foundries.  His responsibilities include silicon, 3D-IC, advanced packaging, thermal mechanical solutions and many other technologies development in Xilinx.

Director of Engineering / AI Chief Scientist, Microelectronics

Dr. Ke Xu got the B.S. and M.S. degrees in Electrical Engineering Department from Fudan University, Shanghai, China, in 2000 and 2003, respectively, and the Ph.D. degree with Outstanding Award from the Department of Electronic Engineering, The Chinese University of Hong Kong in 2007. He was also the Post-doctoral Research Fellow in the Department of Electrical and Computer Engineering at the University of Toronto in 2009.

He served various senior roles as Staff/Algorithm Engineer, Chip Architect, Research Scientist, in different companies from startups to Fortune 500 such as IBM and Qualcomm, in China, Canada, and the USA.  As key R &D member for Snapdragon 810/820/835 development in Qualcomm headquarter in San Diego, he was in charge of artificial intelligence/computer vision system, virtual/augmented reality, and image and video processing system design. He joined ZTE Microelectronics in 2015 as AI Chief Scientist and Director of Engineering, where he is in charge of AI, autonomous driving, AR/VR, and multimedia chip designs. He led an R&D group of more than 100 engineers with tens of technical experts. He developed several multimedia SoCs including smartphone, IPTV, IPC with advanced 28nm technology. He is also the Researcher in the State Key Laboratory of Mobile Network and Mobile Multimedia Technology. He founded the Chengdu R&D center and expanded from 0 to around 50 employees.

SVP & CTO, Besi

Studied Semiconductor Physics and High Vacuum in the Netherlands, started at ASM Europe in 1984 in Front Equipment (Diffusion, PECVD, Epi and Litho). Moved to MRC (Sputter and Etch). Later joined Balzers/Oerlikon responsible for display equipment division and materials division.

Since 2010 active for Besi. Became SVP for Die Attach group in 2014 and current position CTO for Besi.

Director & Principal Analyst, Packaging, Assembly, Substrates & Semiconductor Manufacturing, YOLE

Santosh Kumar is currently working as the Director & Principal Analyst, Packaging, Assembly, Substrates & Semiconductor Manufacturing. He is the author of several reports covering various packaging platforms, equipment, and materials. He received the bachelor and master’s degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer-reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging

CTO, Continental China

As CTO for Continental China;

• Represent Continental China in all relevant technical aspects both internally and externally
• Lead corporate pilot innovation projects and oversee startup programs
• Responsible for cross divisional system development e.g. EE-architecture, intelligent connected vehicle and automated driving
• Build up advanced technology competency across the company: AI, Cyber Security, Robotics etc.
• Lead future technology development with new services and business models beyond the current scope of divisions and BU’s
• Define and implement innovation strategy including method and tools
• Build up and lead new Chongqing R&D hub as general manager
• Lead technical marketing activities to promote our technologies to key stakeholders
• Lead business development activities to seek new technology and business fields, in which the company can generate meaningful business cases and future growth

Education

• Rutgers University, Beijing International Program; EMBA, Beta Gamma Sigma, 2001
• Rice University, Houston, Texas; M.S. Electrical and Computer Engineering, 1993
• Yale University, New Haven, Connecticut; B.S. Electrical Engineering, distinction in major, Cum Laude, 1992

CPO, Nanotronics

Ms. Orlando began working for Nanotronics’ co-founders Matthew and John Putman at their previous company, Tech Pro, Inc. where she played a key role in the hardware development, sales, and customer service. Tech Pro was acquired by Roper Industries in 2008. Ms. Orlando went on to run a division of Duramax, leading projects for major industrial entities, defense contractors, and branches of the military. Ms. Orlando joined Nanotronics as employee number three, where she is currently Chief Product Officer. Ms. Orlando has published several papers in both domestic and international journals, which she has presented at material science conferences and symposia.

SVP & Deputy GM Production and Technology Unit, Renesas Electronics Corporation

Tomomitsu Maoka is Senior Vice President and Deputy General Manager, Production and Technology Unit at Renesas Electronics Corporation, leading its global transformation of manufacturing structure. In addition, he is Chairman for Renesas Electronics China, engaged in activities related with Public Affairs and Industry Relations.

From March 2017 to Mach 2019, he was General Manager of China Business Unit at Renesas Electronics, led China-focused activities to capture growth and innovation opportunities through collaboration with ecosystem partners, to expand manufacturing partnership with China local foundries and assembly manufacturers, to strengthen relationship with government and industry community and to reinforce synergies among various functions of Renesas oriented for China region.

Maoka joined Renesas in 2013 as Vice President of Corporate Planning and led the turnaround of the company after capital injection by Japanese sovereign private equity fund, INCJ. In 2016, He was in charge of General Purpose Analog & Power business of Renesas and led it revenue turnaround until its consolidation with Intersil business which was acquired in 2017 February.

Prior to joining Renesas, Maoka led Post Merger Integration at Lenovo which acquired NECs personal computer business through Joint Venture structure. Prior to Lenovo, Maoka oversaw industrial business in Japan and of strategy development and alliance management in Japan at Infineon Technologies. Prior to Infineon, Maoka worked for A.T. Kearney as management consultant, where he served Japanese major clients in telecommunication, automotive, etc.

Education

• Master of Engineering and Bachelor of Engineering from the University of Tokyo, majored in Aeronautics and Astronautics.

VP, Advanced Packaging Technology and Service, TSMC

Dr. Marvin Liao / 廖德堆博士

Vice President / 副總經理

APTS / 先進封裝技術暨服務

tsmc / 台灣積體電路製造股份有限公司

Education

• Ph.D. Materials Science, University of Texas at Arlington, USA, 1989
• Bachelor Materials Science, Tsing Hua University, Taiwan, 1979

Experience 

• tsmc Advanced Packaging Technology and Service, 2011 – now
• tsmc Special Project, 2009 – 2010
• tsmc Fab 6 Director, 2003 – 2009
• Chartered Semiconductor, Singapore, 1997 – 2002
• Applied Materials, USA, 1994 – 1997
• SGS Thomson Microelectronics (STM), USA, 1990 – 1994

VP 
Adv. Package & Technology Integration, Amkor Technology

Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via and MEMS packaging technologies. He is currently responsible for the development and commercialization of Amkor’s Advanced Wafer Level Fan-Out package technologies, including High-Density Fan-Out and SWIFT^® technology. Curtis is Past General Chair of the International Wafer Level Packaging Conference 2016-2018 and the 2019 General Chair for the IMAPS Symposium on Microelectronics. He has authored numerous technical articles and papers and co-authored a chapter in the recently released book, “Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies”. Curtis has been issued 21 US patents and holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.

SVP Technology & Operations Semiconductor BU, Nepes Corporation

He has been in the semiconductor area for 21 years with specialty of technology & business development in the advanced packaging area such as Fan Out WLP, Wafer level CSP, Flip chip bumping, SiP (System In Packaging) as well as Panel Level Packaging
He has started his work in LG / Hynix for reliability, material & process development of packaging in late of 1990s after he got Ph.D degree of material science engineering in Korea.
After that, he joined nepes Corporation in 2001 as engineering director but also as set up member of 1^st bumping (6 & 8”) OSAT in Korea.  He has also initiated 12” wafer level bumping project in Korea transferring the technology to Singapore working with EDB, Chartered (now Global Foundry) and also UTAC to set up the joint venture as 1^st 12” bumping company in Singapore.  During his staying in Singapore, he has worked with international customers in US, European Fabless, IDM companies and Taiwan foundries.

He has also led the technical marketing team in USA with his expertise and strength of technology, communication skill and engagement experience with customers.  His main strengths are in the leadership in both of R & D and the broad experience in the production line operation as well as business development with his technology background.

In Singapore and Korea, he has involved and led multiple government funded mega project from R & D programs to its commercialization.
Currently he is responsible for Technology & Operations for WLP, Bumping & Test as well as Fan out WLP, Panel Level Package, and SiP business at nepes Corporation Korea as senior vice president taking care of profit & loss in Semiconductor business.

Technology basis major achievement

1. Wafer Level Packaging & Lead free bumping commercialization from ground zero in current company since 2001 (Korea)
2. Technology set up through license deal for Fan out packaging with freescale in 2011 (Singapore)
3. Won the competition for the multi millions ~150 M USD government funded R & D projects as the leader of project or consortium since 2001 (Majority in following section)

Business basis major achievement

1. Main contribution in establishing & growing company of 200 M revenue advanced packaging business (nepes Corporation in Korea)
2. Joint venture deal discussion with EDB UTAC and plant set up of 1^st 12” bumping plant in Singapore with 20 M revenue record company
3. Joint development with Samsung on the small image sensor packing for 1^st camera built in mobile phone 2002
4. Fan Out packaging & Panel Level packaging platform development and launched it to commercial technology platform generating revenue since 2014

Work Experience

1. Present NEPES Corporation
   1. SVP, Technology & operations, Semiconductor BU, nepes Corporation
   2. Responsible for production & engineering of entire Semiconductor business unit
2. 2014 ~ 2015 NEPES US
   1. VP, Technical marketing and program management for North America region
   2. Set up the US sales force operation
   3. Product & technology promotion in north America working as TPM leader with HQ in Korea
3. 2011 ~ 2013 NEPES Corporation
   1. Vice President, Semiconductor BU in NEPES Corporation
   2. New business, product and technology development of 300 mm bumping, SiP
   3. Program manager for Fan out WLP doing customer development, program management
4. 2005~2010 NEPES Singapore (nepes Pte Ltd)
   1. Chief of Technology Officer / Managing Director
   2. 300 mm Semiconductor bumping plant set up and new technology development
   3. Process & equipment set up, line qualification and product qualification
   4. Customer development and new product & technology management (Wafer Foundries in Singapore, Fabless & IDM in US, Korea, Japan)
   5. Lead free & Micro bumping, Wafer level packaging, TSV R & D program with Singapore government body (EDB)
   6. Fan out technology development with freescale (2010~)
5. 2001~2005 NEPES Corporation
   1. Chief of R & D center
   2. General Manager of New business development in Semi BU
   3. Development project of Chip on Wafer SiP, Embedded packaging, 2.5D TSI packaging
6. 1999-2001 Hynix Semiconductor
   1. Module & packaging development group for Wafer level packaging development activities and solder bumping technology works
   2. Memory packaging development with wafer level CSP
   3. Reliability assessment & improvement (package structure, SJR & material development)
7. 1997–1999 LG Semiconductor
   1. Senior Research Engineer in PKG R & D center
   2. Micro BGA development and package reliability engineering
   3. Failure analysis & research on mechanism of it
8. 1997 INHA University
   1. Part time lecturing in INHA polytechnic for 6 months

Vice President R&D, JCET

Mr. Lin holds B.S. degree in Metal Materials & Heat Treatment from Huazhong University of Science and Technology with honor of outstanding graduate, M.S. degree in Composite Materials from Shanghai Jiaotong University, and M.S. degree in Materials Science from University of Rochester, NY, United States. He has over 20 years R&D experience in materials and semiconductor packaging development, especially in wafer level package and advanced packaging. He holds over 100 US patents in the field of semiconductor packaging.

SVP & GM of China Business Unit, Western Digital

Steven Craig is the Senior Vice President and General Manager for China Go-to-Market. He is leading our effort in creating a new China Go-to- Market operating model that will support, strengthening and expanding Western Digital’s ability to address the unique needs of China’s large and growing market. He will be based in Shanghai, China.

Steven has a rich experience and demonstrated leadership in customer support. He was most recently senior vice president of Quality for Western Digital Corporation, who oversaw the quality assurance and customer technical support functions worldwide for all of its brands. Prior to that he was senior vice president of Quality at HGST, and the senior vice president of customer experience at Dot Hill Corporation.

Steven previously spent 11 years at Maxtor Corporation, where he held multiple senior management positions, including vice president of worldwide customer engineering. Prior to joining Maxtor, Steven worked in various engineering positions at Conner Peripherals in the UK and in Houston. Steven earned his Bachelor’s Degree from Fife College of Technology, Scotland, UK.

Senior Principal Analyst, Automotive Semiconductor, IHS Markit

Mr. Phil Amsrud, a senior principal analyst at IHS Markit, covering the automotive semiconductor market in general with a special focus on advanced driver-assistance systems (ADAS) and autonomous driving.

Phil Amsrud is a senior principal analyst for the IHS Markit’s automotive semiconductor research area with a special focus on advanced driver-assistance systems (ADAS) and autonomous driving technologies.

Phil began his career in automotive electronics as a design engineer at GM on their ABS systems. From there he joined Motorola Semiconductor Products Sector supporting Delphi Electronics then became part of Freescale Semiconductor that was spun off from Motorola. At Freescale he managed the field sales and applications engineers supporting Continental Automotive. After obtaining a masters in business, Phil joined ON Semiconductor and was responsible for field sales and applications team in the Americas region supporting Continental Automotive.  Phil also served as new business development manager for the Americas at BAE Systems/Fairchild Imaging prior to joining IHS Markit.

Phil holds both a Bachelor of Science in Electrical Engineering and Master of Science in Business degrees from the University of Wisconsin-Madison, US.

Mustafa Pinarbasi is the CTO and Sr. Vice President of Magnetics Technology at Spin Memory (Previously Spin Transfer Technologies). Before joining Spin Memory in 2013, Dr. Pinarbasi was a CTO and SVP of Technology Development at SoloPower, Advanced Technology Department Manager at Hitachi GST and Distinguished Engineer at IBM. His accomplishments at IBM include the development of the giant magneto-resistance sensor used in the first GMR-based hard disk drives (HDD) and pioneering the adoption of ion beam sputtering technology into the read sensor production. He led the development of tunneling magneto-resistance (TMR) read head processing at Hitachi GST and the development of flexible and light weight solar panels at SoloPower. Dr. Pinarbasi holds a Ph.D. from the University of Illinois at Urbana-Champaign. He is an inventor with over 200 U.S. patents, has authored or co-authored over 30 scientific publications and has received numerous industry awards.

Mr. Ning Chen used to work in the mobile communication industry in Japan for long years. After joined Panasonic in 2003, he has been engaged in the development of advanced sensor solutions for smart systems. He is now the Director of China Technology Center of Industrial Solutions Company.

Ron, who joined CNW in early 2013 after over a decade at DHL, sees himself as customer-centric. He is available day and night to listen and help customers realize that CNW is their most reliable special logistics partner. Ron believes in open communications and making it easy for them to approach CNW with urgent and emergency shipping challenges, no matter how complicated.</span>

And as a big basketball fan and food connoisseur, Ron welcomes the opportunity to enjoy a good meal after a great game.

Hermann Waltl is currently the executive sales and customer support director for EV Group (EVG). In this role, he is responsible for overseeing EVG’s worldwide sales operations across all of the company’s product lines and key markets including Asia Pacific, Europe and North America. Waltl joined EV Group in 2002 as a sales operations manager where he was responsible for all aspects of worldwide contract management and sales administration for three years.

Prior to EVG, he held several management positions at Amdahl Deutschland GmbH (Amdahl Germany Ltd.), including most recently as director of professional services for Central Europe, and country manager for Switzerland and Austria. In this role, he oversaw an organization of 120 employees and provided consulting services to the IT industry. Before that, Waltl served as both a project manager and sales manager at Nixdorf Computer GmbH/Siemens Nixdorf Information Systems in Salzburg, Austria.

Waltl received a master of business administration degree, with an emphasis on business economics and strategic corporate management, from the University of Innsbruck, Austria.

Julio Coppo is currently serving the role of Vice President of Sales and Strategic Business Development for Nanotronics, a technology company that builds robotic, artificially intelligent industrial grade microscopes, including nSpec® and nSpec® 3D. nSpec®’s highly customizable software and hardware, enables these products to serve the semiconductor, material sciences, rubber, pharmaceutical and biotechnology industries. Julio joined Nanotronics in the Fall of 2016 and he oversees the global sales and customer outreach team.

Julio spends his personal time with his children and volunteering in youth enrichment programs such as Assistant Scout Master for Boy Scouts of America, and coaching youth ice hockey.

Previously Julio served as Regional Sales Manager at SUSS MicroTec, Strategic Account Manager for DCG Systems, and Sales and Applications Manager at Schlumberger Automated Test Equipment. Prior to Julio’s entry into the semiconductor industry, Julio served in the U.S. Navy as a Naval Flight Officer, patrolling the skies in the P-3, Orion, Submarine Hunter aircraft.

Mario Morales is the program vice president of IDC’s enabling technologies, storage, and semiconductor research. He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and consumer.

Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.

Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, IBM, GE software, SoftBank, ARM, NXP, and others.

Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.

Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage and memory,sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, accelerated computing architectures, cellular baseband modems, WLAN, WiMAX, cellular broadband, digital consumer, foundry, EMS, intelligent systems, and overall semiconductors.

His career includes past postions with NEC Electronics and Dataquest.

EDUCATIONAL ACCOMPLISHMENTS

• B.S. in Finance and Accounting from San Jose State University
• Fluent in English and Spanish
• Frequent presenter and advisor to CEOs and executive teams across his portfolio of clients
• Strong reputation as an advisor and industry expert on Wall Street
• IDC executive analyst for Intel and Qualcomm
• Frequent speaker, presenter, and moderator at IDC Directions events in Asia and semiconductor industy conferences including ISS, GSA, CASPA, and SEMI