David Fang, CTO – PTI | Topic: Packaging Innovations for Silicon Scaling and Heterogeneous Integration
Packaging Innovations for Silicon Scaling and Heterogeneous Integration
Moore’s law is slowing down but Si scaling will continue. More function will be integrated into SoC with advanced wafers node. Chip is getting small and I/O pitch becomes smaller by Si scaling. Traditional organic substrate couldn’t handle fine I/O pitch. Industry is developing novel advanced chip carrier to support Si scaling. This article will introduce a variety of chip carriers and their advantage and disadvantage. Panel level FO technology could build RDL substrate with fine line and space. It might be one of advanced chip carriers for heterogeneous integration. The latest panel level FO development status will be updated.
Processor and memory will be integrated in a package to improve system performance. HBM is indispensable for embedded memory of HPC. 3D stack with TSV interconnect is used for HBM cube assembly. Conventional testing method couldn’t meet HBM requirement. Have to develop unique memory testing for HBM. The presentation will point out not only the challenge of assembly and testing but also address the solution based on OSAT point of view.