Herbert Oetzibger, CEO – Semsysco |Topic: Heterogeneous Integration in Packaging will require Design Rules and Process Performance that are Equivalent to Backend of the Wafer Fab Design Rules
Electrolytic metal deposition and the supporting wet process steps such as cleaning, dielectric develop, resist develop, resit strip, barrier and seed layer etch are key process steps in the manufacturing of vertical and horizontal interconnections used in today’s PCBs and IC substrates on one hand and advanced packaging applications on the other hand.
In the past both application areas were separated by different substrate formats and feature sizes.
This will change in the future. The increasing demand of higher performance and lower cost will drive the PCBs to fine line plating, down to micron or even sub-micron fine structures and IC- wafer packaging to large substrate formats.
This will require a total new tool set for wet processing and electrolytic plating. This tool set will need to be able to transfer fine line, process capability from wafer scale performance to large substrate scale.
Feature sizes down to 2µm L/S or smaller on substrates as large as 650mm x650mm will require excellent metal thickness uniformity as known from today’s wafer IC manufacturing.
The challenge for the next generation large substrate HVM production tools is in process control, process stability, uniformity, cleanliness, factory automation, APC, SPC, scrap prevention, tool size and last not least CoO.
The wafer level tool performance needs to become a large substrate tool performance. All the learning from the last 20 years on wafer tools need to be integrated on large substrate tools.
The presentation covers studies, result and conclusions in critical performance areas of the plating process and the required wet processes, such as fluid dynamics, uniformity, concentration control, particle control, cleaning and striping efficiencies, fine line resist and dielectric development, residue and particle free handling and processing.
The challenge is, to put wafer scale performance into a large panel tool and maintain a TCoO suitable for commercial product value.