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Jong Heon Kim, SVP Technology & Operations Semiconductor BU – NEPES Corporation | Topic: Ultimate 3D Package Solution by FO / PLP Technology

05 Sep 2019
10:10 – 10:30

Jong Heon Kim, SVP Technology & Operations Semiconductor BU – NEPES Corporation | Topic: Ultimate 3D Package Solution by FO / PLP Technology

Three-dimensional integrated circuit (3D-IC) and 2.5D IC with Si interposer are regarded as promising candidates to overcome the limitations of Moore’s law due to their advantages of lower power consumption, smaller form factor, higher performance, and higher function density. However, the conventional package to package with solder balls may have concerns of solder joint reliability due to CTE mismatching as well as increase in overall package thickness. TSV technology is one of promising solution forperformance, form factor, however it is used in limited area due to high investment cost and low productivity. • nepes proposes Fan-out-based 3D-IC package since it is apromising solution for heterogeneous chips stacking at the panel level process without solder joint so that it can prevent assembly failures and also expected to have excellent electrical characteristics with short interconnect length achieving thin package profile. • The proposed 3D-IC package here is using the Fan-Out platform technology stacking chips at the panel level where the 2nd and subsequent chips are stacked on fan-out reconstituted 1st panel and connected with RDL through deep-via technology.  Also, the prototype of stacked package using nepes’ own Artificial Intelligence is demonstrated and tested. Further more, this technologycanberealizedatalsolargepanellevel packaging which nepes is pursuing actively.