Xin Wu, VP of Silicon Technology – Xilinx | Topic: Moore’s Law, Hetero-integration and Adaptable Compute Acceleration Platform (ACAP)
Moore’s Law provided the power of growth of FPGA (Field Programmable Gate Array) continually in past several decades till 28nm node. Since then although silicon technology still provides scaling and power-performance improvement, the gain become smaller and cost keep increasing. Nevertheless other hetero-integration technologies, such as 3D-ICs, various advanced packaging, as well as better integration of thermal-mechanical solutions, provided continual FPGA capability expansion. These hetero-integrations also allow the integration of other IPs, such as HBM (High Bandwidth Memory) and 3rd-party chip-to-chip possible.
Innovated architectures, designs, software and system solutions are inseparable parts of capacity expansion. The recently starting shipping 7nm Versal ACAP (Adaptive Compute Acceleration Platform) family, brings a new level of capability expansion, based on domain specific adaptive architecture, include ARM scalar engine, more than 2x of programmable engine, DDR interfaces and HBM, SERDEs from 25 to 112Gbps, PCIe and CCIX as well as NOC (Network-On-Chip), both hardware and software solutions. They are optimized for data-center, AI, ML (Machine Learning), 5G, automotive AD/ADAS, edge compute, industrial and emulation, avionics and defense, and many more applications.