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Jong-Heon Kim, NEPES Corporation

SVP Technology & Operations Semiconductor BU

Jong-Heon Kim, NEPES Corporation

SVP Technology & Operations Semiconductor BU

Biography

Career & Experience

He has been in the semiconductor area for 21 years with specialty of technology & business development in the advanced packaging area such as Fan Out WLP, Wafer level CSP, Flip chip bumping, SiP (System In Packaging) as well as Panel Level Packaging
He has started his work in LG / Hynix for reliability, material & process development of packaging in late of 1990s after he got Ph.D degree of material science engineering in Korea.
After that, he joined nepes Corporation in 2001 as engineering director but also as set up member of 1st bumping (6 & 8”) OSAT in Korea.  He has also initiated 12” wafer level bumping project in Korea transferring the technology to Singapore working with EDB, Chartered (now Global Foundry) and also UTAC to set up the joint venture as 1st 12” bumping company in Singapore.  During his staying in Singapore, he has worked with international customers in US, European Fabless, IDM companies and Taiwan foundries.

He has also led the technical marketing team in USA with his expertise and strength of technology, communication skill and engagement experience with customers.  His main strengths are in the leadership in both of R & D and the broad experience in the production line operation as well as business development with his technology background.

In Singapore and Korea, he has involved and led multiple government funded mega project from R & D programs to its commercialization.
Currently he is responsible for Technology & Operations for WLP, Bumping & Test as well as Fan out WLP, Panel Level Package, and SiP business at nepes Corporation Korea as senior vice president taking care of profit & loss in Semiconductor business.

 

Technology basis major achievement

  1. Wafer Level Packaging & Lead free bumping commercialization from ground zero in current company since 2001 (Korea)
  2. Technology set up through license deal for Fan out packaging with freescale in 2011 (Singapore)
  3. Won the competition for the multi millions ~150 M USD government funded R & D projects as the leader of project or consortium since 2001 (Majority in following section)

Business basis major achievement

  1. Main contribution in establishing & growing company of 200 M revenue advanced packaging business (nepes Corporation in Korea)
  2. Joint venture deal discussion with EDB UTAC and plant set up of 1st 12” bumping plant in Singapore with 20 M revenue record company
  3. Joint development with Samsung on the small image sensor packing for 1st camera built in mobile phone 2002
  4. Fan Out packaging & Panel Level packaging platform development and launched it to commercial technology platform generating revenue since 2014

Work Experience

  1. Present NEPES Corporation
    1. SVP, Technology & operations, Semiconductor BU, nepes Corporation
    2. Responsible for production & engineering of entire Semiconductor business unit
  2. 2014 ~ 2015 NEPES US
    1. VP, Technical marketing and program management for North America region
    2. Set up the US sales force operation
    3. Product & technology promotion in north America working as TPM leader with HQ in Korea
  3. 2011 ~ 2013 NEPES Corporation
    1. Vice President, Semiconductor BU in NEPES Corporation
    2. New business, product and technology development of 300 mm bumping, SiP
    3. Program manager for Fan out WLP doing customer development, program management
  4. 2005~2010 NEPES Singapore (nepes Pte Ltd)
    1. Chief of Technology Officer / Managing Director
    2. 300 mm Semiconductor bumping plant set up and new technology development
    3. Process & equipment set up, line qualification and product qualification
    4. Customer development and new product & technology management (Wafer Foundries in Singapore, Fabless & IDM in US, Korea, Japan)
    5. Lead free & Micro bumping, Wafer level packaging, TSV R & D program with Singapore government body (EDB)
    6. Fan out technology development with freescale (2010~)
  5. 2001~2005 NEPES Corporation
    1. Chief of R & D center
    2. General Manager of New business development in Semi BU
    3. Development project of Chip on Wafer SiP, Embedded packaging, 2.5D TSI packaging
  6. 1999-2001 Hynix Semiconductor
    1. Module & packaging development group for Wafer level packaging development activities and solder bumping technology works
    2. Memory packaging development with wafer level CSP
    3. Reliability assessment & improvement (package structure, SJR & material development)
  7. 19971999 LG Semiconductor
    1. Senior Research Engineer in PKG R & D center
    2. Micro BGA development and package reliability engineering
    3. Failure analysis & research on mechanism of it
  8. 1997 INHA University
    1. Part time lecturing in INHA polytechnic for 6 months

All sessions by Jong-Heon Kim, NEPES Corporation