Juergen Wolf received a M.S. degree in Electrical Engineering. In 1994, M. Juergen joined Fraunhofer Institute for Reliability and Microintegration IZM and worked e.g. as group & project manager in the field of wafer level packaging and system in package. Since 2011 he is head of the department Wafer Level System Integration and also head of “ASSID – All Silicon System Integration Dresden” with its 300 mm WL process line. He is involved in a number of research projects on european and international level. Wolf is representative in ITRS/HIR, member of IEEE and SMTA and involved in ENIAC JU, Catrene, EPOSS, Euripides². He has (co) authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.